22-6 Vol. 3B

ARCHITECTURE COMPATIBILITY

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ID (identification flag), bit 21. 

The AC flag (bit 18) was added to the EFLAGS register in the Intel486 processor.

22.16.1  Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors

The following bits in the EFLAGS register that can be used to differentiate between the 32-bit IA-32 processors:

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Bit 18 (the AC flag) can be used to distinguish an Intel386 processor from the P6 family, Pentium, and Intel486 
processors. Since it is not implemented on the Intel386 processor, it will always be clear.

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Bit 21 (the ID flag) indicates whether an application can execute the CPUID instruction. The ability to set and 
clear this bit indicates that the processor is a P6 family or Pentium processor. The CPUID instruction can then 
be used to determine which processor. 

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Bits 19 (the VIF flag) and 20 (the VIP flag) will always be zero on processors that do not support virtual mode 
extensions, which includes all 32-bit processors prior to the Pentium processor.

See Chapter 19, “Processor Identification and Feature Determination,” in the Intel® 64 and IA-32 Architectures 
Software Developer’s Manual, Volume 1, for more information on identifying processors.

22.17 STACK 

OPERATIONS

This section identifies the differences in stack implementation between the various IA-32 processors.

22.17.1 PUSH 

SP

The P6 family, Pentium, Intel486, Intel386, and Intel 286 processors push a different value on the stack for a PUSH 
SP instruction than the 8086 processor. The 32-bit processors push the value of the SP register before it is decre-
mented as part of the push operation; the 8086 processor pushes the value of the SP register after it is decre-
mented. If the value pushed is important, replace PUSH SP instructions with the following three instructions:

PUSH BP
MOV  BP, SP
XCHG BP, [BP] 

This code functions as the 8086 processor PUSH SP instruction on the P6 family, Pentium, Intel486, Intel386, and 
Intel 286 processors.

22.17.2  EFLAGS Pushed on the Stack

The setting of the stored values of bits 12 through 15 (which includes the IOPL field and the NT flag) in the EFLAGS 
register by the PUSHF instruction, by interrupts, and by exceptions is different with the 32-bit IA-32 processors 
than with the 8086 and Intel 286 processors. The differences are as follows:

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8086 processor—bits 12 through 15 are always set.

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Intel 286 processor—bits 12 through 15 are always cleared in real-address mode. 

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32-bit processors in real-address mode—bit 15 (reserved) is always cleared, and bits 12 through 14 have the 
last value loaded into them.

22.18 X87 

FPU

This section addresses the issues that must be faced when porting floating-point software designed to run on 
earlier IA-32 processors and math coprocessors to a Pentium 4, Intel Xeon, P6 family, or Pentium processor with 
integrated x87 FPU. To software, a Pentium 4, Intel Xeon, or P6 family processor looks very much like a Pentium 
processor. Floating-point software which runs on a Pentium or Intel486 DX processor, or on an Intel486 SX