Vol. 3C 35-215

MODEL-SPECIFIC REGISTERS (MSRS)

35.12.1   Additional Uncore PMU MSRs in the Intel

®

 Xeon

®

 Processor E5 v3 Family

Intel Xeon Processor E5 v3 and E7 v3 family are based on the Haswell-E microarchitecture. The MSR-based uncore 
PMU interfaces are listed in Table 35-31. For complete detail of the uncore PMU, refer to Intel Xeon Processor E5 v3 
Product Family Uncore Performance Monitoring Guide. These processors have a CPUID signature with 
DisplayFamily_DisplayModel of 06_3FH.

62

Unavailable: If 1, indicates data for this RMID is not available or not 

monitored for this resource or RMID.

63

Error: If 1, indicates and unsupported RMID or event type was 

written to IA32_PQR_QM_EVTSEL.

C8FH

3215

IA32_PQR_ASSOC

THREAD

Resource Association Register (R/W).

9:0

RMID 

63: 10

Reserved

See Table 35-18, Table 35-27 for other MSR definitions applicable to processors with CPUID signature 06_3FH.

NOTES:

1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the fac-

tory-set configuration is dependent on features specific to the processor and the platform.

Table 35-31.  Uncore PMU MSRs in Intel® Xeon® Processor E5 v3 Family

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec

700H

MSR_PMON_GLOBAL_CTL

Package

Uncore perfmon per-socket global control.

701H

MSR_PMON_GLOBAL_STATUS

Package

Uncore perfmon per-socket global status.

702H

MSR_PMON_GLOBAL_CONFIG

Package

Uncore perfmon per-socket global configuration.

703H

MSR_U_PMON_UCLK_FIXED_CTL

Package

Uncore U-box UCLK fixed counter control

704H

MSR_U_PMON_UCLK_FIXED_CTR

Package

Uncore U-box UCLK fixed counter 

705H

MSR_U_PMON_EVNTSEL0

Package

Uncore U-box perfmon event select for U-box counter 0.

706H

MSR_U_PMON_EVNTSEL1

Package

Uncore U-box perfmon event select for U-box counter 1.

708H

MSR_U_PMON_BOX_STATUS

Package

Uncore U-box perfmon U-box wide status.

709H

MSR_U_PMON_CTR0

Package

Uncore U-box perfmon counter 0

70AH

MSR_U_PMON_CTR1

Package

Uncore U-box perfmon counter 1

710H

MSR_PCU_PMON_BOX_CTL

Package

Uncore PCU perfmon for PCU-box-wide control

711H

MSR_PCU_PMON_EVNTSEL0

Package

Uncore PCU perfmon event select for PCU counter 0.

712H

MSR_PCU_PMON_EVNTSEL1

Package

Uncore PCU perfmon event select for PCU counter 1.

713H

MSR_PCU_PMON_EVNTSEL2

Package

Uncore PCU perfmon event select for PCU counter 2.

714H

MSR_PCU_PMON_EVNTSEL3

Package

Uncore PCU perfmon event select for PCU counter 3.

715H

MSR_PCU_PMON_BOX_FILTER

Package

Uncore PCU perfmon box-wide filter.

716H

MSR_PCU_PMON_BOX_STATUS

Package

Uncore PCU perfmon box wide status.

Table 35-30.  Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family

Register 

Address

Register Name

Scope

Bit Description

 Hex

Dec