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Vol. 3D A-3

VMX CAPABILITY REPORTING FACILITY

A.3.1  

Pin-Based VM-Execution Controls

The IA32_VMX_PINBASED_CTLS MSR (index 481H) reports on the allowed settings of most of the pin-based 
VM-execution controls (see Section 24.6.1):

Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the pin-based 
VM-execution controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if 
control X is 0.
Exceptions are made for the pin-based VM-execution controls in the default1 class (see Appendix A.2). These 
are bits 1, 2, and 4; the corresponding bits of the IA32_VMX_PINBASED_CTLS MSR are always read as 1. The 
treatment of these controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any pin-based VM-execution control in 

the default1 class is 0.

— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PINBASED_CTLS MSR (see 

below) reports which of the pin-based VM-execution controls in the default1 class can be 0 on VM entry.

Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in 
the MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.

If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PINBASED_CTLS MSR (index 48DH) 
reports on the allowed settings of all of the pin-based VM-execution controls:

Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR 
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.

Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the 
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.

It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the pin-
based VM-execution controls:

If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the pin-based 
VM-execution controls is contained in the IA32_VMX_PINBASED_CTLS MSR. (The 
IA32_VMX_TRUE_PINBASED_CTLS MSR is not supported.)

If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the pin-based 
VM-execution controls is contained in the IA32_VMX_TRUE_PINBASED_CTLS MSR. Assuming that software 
knows that the default1 class of pin-based VM-execution controls contains bits 1, 2, and 4, there is no need for 
software to consult the IA32_VMX_PINBASED_CTLS MSR.

A.3.2  

Primary Processor-Based VM-Execution Controls

The IA32_VMX_PROCBASED_CTLS MSR (index 482H) reports on the allowed settings of most of the primary 
processor-based VM-execution controls (see Section 24.6.2):

Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the primary 
processor-based VM-execution controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 
1, VM entry fails if control X is 0.
Exceptions are made for the primary processor-based VM-execution controls in the default1 class (see 
Appendix A.2). These are bits 1, 4–6, 8, 13–16, and 26; the corresponding bits of the 
IA32_VMX_PROCBASED_CTLS MSR are always read as 1. The treatment of these controls by VM entry is 
determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any of the primary processor-based VM-

execution controls in the default1 class is 0.

— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PROCBASED_CTLS MSR (see 

below) reports which of the primary processor-based VM-execution controls in the default1 class can be 0 
on VM entry.

Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the 
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.