17-58 Vol. 3B
DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES
17.17.3.4 Class of Service to Cache Mask Association: Common Across Allocation Features
After configuring the available classes of service with the preferred set of capacity bitmasks, the OS/VMM can set
the IA32_PQR_ASSOC.COS of a logical processor to the class of service with the desired CBM when a thread
context switch occurs. This allows the OS/VMM to indicate which class of service an executing thread/VM belongs
within. Each logical processor contains an instance of the IA32_PQR_ASSOC register at MSR location 0C8FH, and
Figure 17-34 shows the bit field layout for this register. Bits[63:32] contain the COS field for each logical processor.
Note that placing the RMID field within the same PQR register enables both RMID and CLOS to be swapped at
context swap time for simultaneous use of monitoring and allocation features with a single register write for effi-
ciency.
When CDP is enabled, Specifying a COS value in IA32_PQR_ASSOC.COS greater than MAX_COS_CDP =(
CPUID.(EAX=10H, ECX=1):EDX[15:0] >> 1) will cause undefined performance impact to code and data fetches.
Note that if the IA32_PQR_ASSOC.COS is never written then the CAT capability defaults to using COS 0, which in
turn is set to the default mask in IA32_L3_MASK_0 - which is all “1”s (on reset). This essentially disables the
enforcement feature by default or for legacy operating systems and software.
See Section 17.17.5, “Cache Allocation Technology Programming Considerations” for important COS programming
considerations including maximum values when using CAT and CDP.
17.17.4 Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology
CDP is an extension of CAT. The presence of the CDP feature is enumerated via CPUID.(EAX=10H,
ECX=1):ECX.CDP[bit 2] (see Figure 17-32). Most of the CPUID.(EAX=10H, ECX=1) sub-leaf data that applies to
CAT also apply to CDP. However, CPUID.(EAX=10H, ECX=1):EDX.COS_MAX_CAT specifies the maximum COS
applicable to CAT-only operation. For CDP operations, COS_MAX_CDP is equal to (CPUID.(EAX=10H,
ECX=1):EDX.COS_MAX_CAT >>1).
If CPUID.(EAX=10H, ECX=1):ECX.CDP[bit 2] =1, the processor supports CDP and provides a new MSR
IA32_L3_QOS_CFG at address 0C81H. The layout of IA32_L3_QOS_CFG is shown in Figure 17-36. The bit field
definition of IA32_L3_QOS_CFG are:
•
Bit 0: L3 CDP Enable. If set, enables CDP, maps CAT mask MSRs into pairs of Data Mask and Code Mask MSRs.
The maximum allowed value to write into IA32_PQR_ASSOC.COS is COS_MAX_CDP.
•
Bits 63:1: Reserved. Attempts to write to reserved bits result in a #GP(0).
IA32_L3_QOS_CFG default values are all 0s at RESET, the mask MSRs are all 1s. Hence. all logical processors are
initialized in COS0 allocated with the entire L3 with CDP disabled, until software programs CAT and CDP.
Before enabling or disabling CDP, software should write all 1's to all of the CAT/CDP masks to ensure proper
behavior (e.g., the IA32_L3_QOS_Mask_n set of MSRs). When enabling CDP, software should also ensure that only
COS number which are valid in CDP operation is used, otherwise undefined behavior may result. For instance in a
case with 16 CAT COS, since COS are reduced by half when CDP is enabled, software should ensure that only COS
0-7 are in use before enabling CDP (along with writing 1's to all mask bits before enabling or disabling CDP).
Software should also account for the fact that mask interpretations change when CDP is enabled or disabled,
meaning for instance that a CAT mask for a given COS may become a code mask for a different Class of Service
Figure 17-36. Layout of IA32_L3_QOS_CFG
0
2
63
1
Reserved
IA32_L3_QOS_CFG
3
L3 CDP Enable