Vol. 3A 9-9

PROCESSOR MANAGEMENT AND INITIALIZATION

changed by using the LIDT instruction to change the base address value in the IDTR. Software initialization code 
needs to load interrupt- and exception-handler pointers into the IDT before interrupts can be enabled. 
The actual interrupt- and exception-handler code can be contained either in EPROM or RAM; however, the code 
must be located within the 1-MByte addressable range of the processor in real-address mode. If the handler code 
is to be stored in RAM, it must be loaded along with the IDT.

9.7.2 

NMI Interrupt Handling

The NMI interrupt is always enabled (except when multiple NMIs are nested). If the IDT and the NMI interrupt 
handler need to be loaded into RAM, there will be a period of time following hardware reset when an NMI interrupt 
cannot be handled. During this time, hardware must provide a mechanism to prevent an NMI interrupt from halting 
code execution until the IDT and the necessary NMI handler software is loaded. Here are two examples of how 
NMIs can be handled during the initial states of processor initialization:

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A simple IDT and NMI interrupt handler can be provided in EPROM. This allows an NMI interrupt to be handled 
immediately after reset initialization.

•

The system hardware can provide a mechanism to enable and disable NMIs by passing the NMI# signal through 
an AND gate controlled by a flag in an I/O port. Hardware can clear the flag when the processor is reset, and 
software can set the flag when it is ready to handle NMI interrupts.

9.8 

SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION

The processor is placed in real-address mode following a hardware reset. At this point in the initialization process, 
some basic data structures and code modules must be loaded into physical memory to support further initialization 
of the processor, as described in Section 9.7, “Software Initialization for Real-Address Mode Operation.” Before the 
processor can be switched to protected mode, the software initialization code must load a minimum number of 
protected mode data structures and code modules into memory to support reliable operation of the processor in 
protected mode. These data structures include the following:

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A IDT.

•

A GDT.

•

A TSS.

•

(Optional) An LDT.

•

If paging is to be used, at least one page directory and one page table.

•

A code segment that contains the code to be executed when the processor switches to protected mode.

•

One or more code modules that contain the necessary interrupt and exception handlers.

Software initialization code must also initialize the following system registers before the processor can be switched 
to protected mode:

•

The GDTR.

•

(Optional.) The IDTR. This register can also be initialized immediately after switching to protected mode, prior 
to enabling interrupts.

•

Control registers CR1 through CR4.

•

(Pentium 4, Intel Xeon, and P6 family processors only.) The memory type range registers (MTRRs).

With these data structures, code modules, and system registers initialized, the processor can be switched to 
protected mode by loading control register CR0 with a value that sets the PE flag (bit 0).

9.8.1 

Protected-Mode System Data Structures

The contents of the protected-mode system data structures loaded into memory during software initialization, 
depend largely on the type of memory management the protected-mode operating-system or executive is going to 
support: flat, flat with paging, segmented, or segmented with paging.