Vol. 3A 13-5

SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES

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System Exceptions:
— Invalid-opcode exception (#UD). This exception is generated when executing SSE instructions under the 

following conditions:

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SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 feature flags returned by CPUID are set to 0. This condition 

does not affect the CLFLUSH instruction, nor POPCNT.

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The CLFSH feature flag returned by the CPUID instruction is set to 0. This exception condition only 

pertains to the execution of the CLFLUSH instruction. 

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The POPCNT feature flag returned by the CPUID instruction is set to 0. This exception condition only 

pertains to the execution of the POPCNT instruction. 

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The EM flag (bit 2) in control register CR0 is set to 1, regardless of the value of TS flag (bit 3) of CR0. 

This condition does not affect the PAUSE, PREFETCHh, MOVNTI, SFENCE, LFENCE, MFENCE, CLFLUSH, 
CRC32 and POPCNT instructions.

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The OSFXSR flag (bit 9) in control register CR4 is set to 0. This condition does not affect the PSHUFW, 

MOVNTQ, MOVNTI, PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, CLFLUSH, CRC32 and POPCNT 
instructions.

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Executing an instruction that causes a SIMD floating-point exception when the OSXMMEXCPT flag (bit 

10) in control register CR4 is set to 0. See Section 13.4.1, “Using the TS Flag to Control the Saving of 
the x87 FPU and SSE State.”

— Device not available (#NM). This exception is generated by executing a SSE instruction when the TS flag 

(bit 3) of CR0 is set to 1.

Other exceptions can occur during delivery of the above exceptions.

13.1.5 

Providing a Handler for the SIMD Floating-Point Exception (#XM)

SSE instructions do not generate numeric exceptions on packed integer operations. They can generate the 
following numeric (SIMD floating-point) exceptions on packed and scalar single-precision and double-precision 
floating-point operations. 

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Invalid operation (#I)

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Divide-by-zero (#Z)

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Denormal operand (#D)

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Numeric overflow (#O)

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Numeric underflow (#U)

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Inexact result (Precision) (#P)

These SIMD floating-point exceptions (with the exception of the denormal operand exception) are defined in the 
IEEE Standard 754 for Binary Floating-Point Arithmetic and represent the same conditions that cause x87 FPU 
floating-point error exceptions (#MF) to be generated for x87 FPU instructions.
Each of these exceptions can be masked, in which case the processor returns a reasonable result to the destination 
operand without invoking an exception handler. However, if any of these exceptions are left unmasked, detection 
of the exception condition results in a SIMD floating-point exception (#XM) being generated. See Chapter 6, 
“Interrupt 19—SIMD Floating-Point Exception (#XM).”
To handle unmasked SIMD floating-point exceptions, the operating system or executive must provide an exception 
handler. The section titled “SSE and SSE2 SIMD Floating-Point Exceptions” in Chapter 11, “Programming with 
Streaming SIMD Extensions 2 (SSE2),” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, 
Volume 1, describes the SIMD floating-point exception classes and gives suggestions for writing an exception 
handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point exceptions (#XM), the OSXM-
MEXCPT flag (bit 10) must be set in control register CR4.