Vol. 3A 11-13

MEMORY CACHE CONTROL

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NW flag, bit 29 of control register CR0 — Controls the write policy for system memory locations (see 
Section 2.5, “Control Registers”). If the NW and CD flags are clear, write-back is enabled for the whole of 
system memory, but may be restricted for individual pages or regions of memory by other cache-control 
mechanisms. Table 11-5 shows how the other combinations of CD and NW flags affects caching.

NOTES

For the Pentium 4 and Intel Xeon processors, the NW flag is a don’t care flag; that is, when the CD 
flag is set, the processor uses the no-fill cache mode, regardless of the setting of the NW flag.
For Intel Atom processors, the NW flag is a don’t care flag; that is, when the CD flag is set, the 
processor disables caching, regardless of the setting of the NW flag.
For the Pentium processor, when the L1 cache is disabled (the CD and NW flags in control register 
CR0 are set), external snoops are accepted in DP (dual-processor) systems and inhibited in unipro-
cessor systems. 
When snoops are inhibited, address parity is not checked and APCHK# is not asserted for a corrupt 
address; however, when snoops are accepted, address parity is checked and APCHK# is asserted 
for corrupt addresses.

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PCD and PWT flags in paging-structure entries — Control the memory type used to access paging 
structures and pages (see Section 4.9, “Paging and Memory Typing”).

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PCD and PWT flags in control register CR3 — Control the memory type used to access the first paging 
structure of the current paging-structure hierarchy (see Section 4.9, “Paging and Memory Typing”).

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G (global) flag in the page-directory and page-table entries (introduced to the IA-32 architecture in 
the P6 family processors) — Controls the flushing of TLB entries for individual pages. See Section 4.10, 
“Caching Translation Information,” for more information about this flag.

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PGE (page global enable) flag in control register CR4 — Enables the establishment of global pages with 
the G flag. See Section 4.10, “Caching Translation Information,” for more information about this flag.

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Memory type range registers (MTRRs) (introduced in P6 family processors) — Control the type of 
caching used in specific regions of physical memory. Any of the caching types described in Section 11.3, 
“Methods of Caching Available,” can be selected. See Section 11.11, “Memory Type Range Registers (MTRRs),” 
for a detailed description of the MTRRs.

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Page Attribute Table (PAT) MSR (introduced in the Pentium III processor) — Extends the memory 
typing capabilities of the processor to permit memory types to be assigned on a page-by-page basis (see 
Section 11.12, “Page Attribute Table (PAT)”).

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Third-Level Cache Disable flag, bit 6 of the IA32_MISC_ENABLE MSR (Available only in processors 
based on Intel NetBurst microarchitecture) — Allows the L3 cache to be disabled and enabled, indepen-
dently of the L1 and L2 caches. 

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KEN# and WB/WT# pins (Pentium processor) — Allow external hardware to control the caching method 
used for specific areas of memory. They perform similar (but not identical) functions to the MTRRs in the P6 
family processors.

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PCD and PWT pins (Pentium processor) — These pins (which are associated with the PCD and PWT flags in 
control register CR3 and in the page-directory and page-table entries) permit caching in an external L2 cache 
to be controlled on a page-by-page basis, consistent with the control exercised on the L1 cache of these 
processors. The P6 and more recent processor families do not provide these pins because the L2 cache in 
internal to the chip package.

11.5.2 

Precedence of Cache Controls

The cache control flags and MTRRs operate hierarchically for restricting caching. That is, if the CD flag is set, 
caching is prevented globally (see Table 11-5). If the CD flag is clear, the page-level cache control flags and/or the 
MTRRs can be used to restrict caching. If there is an overlap of page-level and MTRR caching controls, the mecha-
nism that prevents caching has precedence. For example, if an MTRR makes a region of system memory uncache-
able, a page-level caching control cannot be used to enable caching for a page in that region. The converse is also