Vol. 3B 17-11

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

Xeon, Pentium M, Intel

®

 Core™ Solo, Intel

®

 Core™ Duo, Intel

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 Core™2 Duo, Intel

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 Core™ i7 and Intel

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 Atom™ 

processors to allow logging of branch trace messages in a branch trace store (BTS) buffer in memory. 
See the following sections for processor specific implementation of last branch, interrupt and exception recording:

— Section 17.5, “Last Branch, Interrupt, and Exception Recording (Intel® Core™ 2 Duo and Intel® Atom™ 

Processors)”

— Section 17.6, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on 

Goldmont Microarchitecture”

— Section 17.7, “Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchi-

tecture code name Nehalem”

— Section 17.8, “Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchi-

tecture code name Sandy Bridge”

— Section 17.9, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Haswell 

Microarchitecture”

— Section 17.10, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on 

Skylake Microarchitecture”

— Section 17.12, “Last Branch, Interrupt, and Exception Recording (Intel® Core™ Solo and Intel® Core™

 

Duo Processors)”

— Section 17.13, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors)”
— Section 17.14, “Last Branch, Interrupt, and Exception Recording (P6 Family Processors)”

The following subsections of Section 17.4 describe common features of profiling branches. These features are 
generally enabled using the IA32_DEBUGCTL MSR (older processor may have implemented a subset or model-
specific features, see definitions of MSR_DEBUGCTLA, MSR_DEBUGCTLB, MSR_DEBUGCTL).

17.4.1 IA32_DEBUGCTL 

MSR

The IA32_DEBUGCTL MSR provides bit field controls to enable debug trace interrupts, debug trace stores, trace 
messages enable, single stepping on branches, last branch record recording, and to control freezing of LBR stack 
or performance counters on a PMI request. IA32_DEBUGCTL MSR is located at register address 01D9H. 
See Figure 17-3 for the MSR layout and the bullets below for a description of the flags:

•

LBR (last branch/interrupt/exception) flag (bit 0) — When set, the processor records a running trace of 
the most recent branches, interrupts, and/or exceptions taken by the processor (prior to a debug exception 
being generated) in the last branch record (LBR) stack. For more information, see the Section 17.5.1, “LBR 
Stack” (Intel

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 Core™2 Duo and Intel

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 Atom™ Processor Family) and Section 17.7.1, “LBR Stack” (processors 

based on Intel

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 Microarchitecture code name Nehalem).

•

BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS 
register as a “single-step on branches” flag rather than a “single-step on instructions” flag. This mechanism 
allows single-stepping the processor on taken branches. See Section 17.4.3, “Single-Stepping on Branches,” 
for more information about the BTF flag.

•

TR (trace message enable) flag (bit 6) — When set, branch trace messages are enabled. When the 
processor detects a taken branch, interrupt, or exception; it sends the branch record out on the system bus as 
a branch trace message (BTM). See Section 17.4.4, “Branch Trace Messages,” for more information about the 
TR flag.

•

BTS (branch trace store) flag (bit 7) — When set, the flag enables BTS facilities to log BTMs to a memory-
resident BTS buffer that is part of the DS save area. See Section 17.4.9, “BTS and DS Save Area.”

•

BTINT (branch trace interrupt) flag (bit 8) — When set, the BTS facilities generate an interrupt when the 
BTS buffer is full. When clear, BTMs are logged to the BTS buffer in a circular fashion. See Section 17.4.5, “Branch 
Trace Store (BTS),” for a description of this mechanism.