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18-64 Vol. 3B

PERFORMANCE MONITORING

Details of the uncore performance monitoring facility of Intel Xeon Processor E5 v2 and Intel Xeon Processor E7 v2
families are available in “Intel® Xeon® Processor E5 v2 and E7 v2 Uncore Performance Monitoring Programming
Reference Manual”. The MSR-based uncore PMU interfaces are listed in Table 35-26.

18.11 4TH

GENERATION

INTEL

CORE

™

PROCESSOR PERFORMANCE

MONITORING FACILITY

The 4th generation Intel

Core™ processor and Intel

Xeon

processor E3-1200 v3 product family are based on

the Haswell microarchitecture. The core PMU supports architectural performance monitoring capability with version
ID 3 (see Section 18.2.3) and a host of non-architectural monitoring capabilities.
Architectural performance monitoring version 3 capabilities are described in Section 18.2.3.
The core PMU’s capability is similar to those described in Section 18.9 through Section 18.9.5, with some differ-
ences and enhancements summarized in Table 18-42. Additionally, the core PMU provides some enhancement to
support performance monitoring when the target workload contains instruction streams using Intel

Transactional

Synchronization Extensions (TSX), see

Section 18.11.5. For details of Intel TSX, see Chapter 16, “Programming with

Intel® Transactional Synchronization Extensions” of Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1.

Table 18-42. Core PMU Comparison

Box

Intel® microarchitecture code

name Haswell

Intel® microarchitecture code

name Sandy Bridge

Comment

# of Fixed counters per thread