15-6 Vol. 3B

MACHINE-CHECK ARCHITECTURE

NOTE

For P6 family processors, processors based on Intel Core microarchitecture (excluding those on 
which on which CPUID reports DisplayFamily_DisplayModel as 06H_1AH and onward): the 
operating system or executive software must not modify the contents of the IA32_MC0_CTL MSR. 
This MSR is internally aliased to the EBL_CR_POWERON MSR and controls platform-specific error 
handling features. System specific firmware (the BIOS) is responsible for the appropriate initial-
ization of the IA32_MC0_CTL MSR. P6 family processors only allow the writing of all 1s or all 0s to 
the IA32_MCi_CTL MSR.

15.3.2.2   IA32_MCi_STATUS MSRS

Each IA32_MCi_STATUS MSR contains information related to a machine-check error if its VAL (valid) flag is set (see 
Figure 15-6). Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 
1s to them causes a general-protection exception.

NOTE

Figure 15-6 depicts the IA32_MCi_STATUS MSR when IA32_MCG_CAP[24] = 1, 
IA32_MCG_CAP[11] = 1 and IA32_MCG_CAP[10] = 1. When IA32_MCG_CAP[24] = 0 and 
IA32_MCG_CAP[11] = 1, bits 56:55 is reserved and bits 54:53 for threshold-based error reporting. 
When IA32_MCG_CAP[11] = 0, bits 56:53 are part of the “Other Information” field. The use of bits 
54:53 for threshold-based error reporting began with Intel Core Duo processors, and is currently 
used for cache memory. See Section 15.4, “Enhanced Cache Error reporting,” for more information. 
When IA32_MCG_CAP[10] = 0, bits 52:38 are part of the “Other Information” field. The use of bits 
52:38 for corrected MC error count is introduced with Intel 64 processor on which CPUID reports 
DisplayFamily_DisplayModel as 06H_1AH. 

Where:

•

MCA (machine-check architecture) error code field, bits 15:0 — Specifies the machine-check archi-
tecture-defined error code for the machine-check error condition detected. The machine-check architecture-
defined error codes are guaranteed to be the same for all IA-32 processors that implement the machine-check 
architecture. See Section 15.9, “Interpreting the MCA Error Codes,” and Chapter 16, “Interpreting Machine-
Check Error Codes”, for information on machine-check error codes. 

•

Model-specific error code field, bits 31:16 — Specifies the model-specific error code that uniquely 
identifies the machine-check error condition detected. The model-specific error codes may differ among IA-32 
processors for the same machine-check error condition. See Chapter 16, “Interpreting Machine-Check Error 
Codes”for information on model-specific error codes.

•

Reserved, Error Status, and Other Information fields, bits 56:32 — 

•

If IA32_MCG_CAP.MCG_EMC_P[bit 25] is 0, bits 37:32 contain “Other Information” that is implemen-

tation-specific and is not part of the machine-check architecture.

•

If IA32_MCG_CAP.MCG_EMC_P is 1, “Other Information” is in bits 36:32. If bit 37 is 0, system firmware 

has not changed the contents of IA32_MCi_STATUS. If bit 37 is 1, system firmware may have edited the 
contents of IA32_MCi_STATUS. 

•

If IA32_MCG_CAP.MCG_CMCI_P[bit 10] is 0, bits 52:38 also contain “Other Information” (in the same 

sense as bits 37:32).

Figure 15-5.  IA32_MCi_CTL Register

EEj—Error reporting enable flag

63

0

1

2

3

E
E

0
1

E
E

0
2

E
E

0
0

E
E

6
1

E
E

6
2

E
E

6
3

62 61

. . . . .

         (where j is 00 through 63)