A-8 Vol. 3D

VMX CAPABILITY REPORTING FACILITY

— If bit 42 is read as 1, the all-context INVVPID type is supported.
— If bit 43 is read as 1, the single-context-retaining-globals INVVPID type is supported.

•

Bits 5:1, bit 7, bits 13:9, bit 15, bits 19:18, bits 24:22, bits 31:27, bits 39:33, and bits 63:44 are reserved 
and are read as 0.

The IA32_VMX_EPT_VPID_CAP MSR exists only on processors that support the 1-setting of the “activate secondary 
controls” VM-execution control (only if bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1) and that support 
either the 1-setting of the “enable EPT” VM-execution control (only if bit 33 of the IA32_VMX_PROCBASED_CTLS2 
MSR is 1) or the 1-setting of the “enable VPID” VM-execution control (only if bit 37 of the 
IA32_VMX_PROCBASED_CTLS2 MSR is 1).

A.11 VM 

FUNCTIONS

The IA32_VMX_VMFUNC MSR (index 491H) reports on the allowed settings of the VM-function controls (see 
Section 24.6.14). VM entry allows bit X of the VM-function controls to be 1 if bit X in the MSR is set to 1; if bit X in 
the MSR is cleared to 0, VM entry fails if bit X of the VM-function controls, the “activate secondary controls” primary 
processor-based VM-execution control, and the “enable VM functions” secondary processor-based VM-execution 
control are all 1.
The IA32_VMX_VMFUNC MSR exists only on processors that support the 1-setting of the “activate secondary 
controls” VM-execution control (only if bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1) and the 1-setting of 
the “enable VM functions” secondary processor-based VM-execution control (only if bit 45 of the 
IA32_VMX_PROCBASED_CTLS2 MSR is 1).