Vol. 3A 10-37

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

Once the local APIC has been switched to x2APIC mode (EN = 1, EXTD = 1), switching back to xAPIC mode would 
require system software to disable the local APIC unit. Specifically, attempting to write a value to the 
IA32_APIC_BASE MSR that has (EN= 1, EXTD = 0) when the local APIC is enabled and in x2APIC mode causes a 
general-protection exception. Once bit 10 in IA32_APIC_BASE MSR is set, the only way to leave x2APIC mode 
using IA32_APIC_BASE would require a WRMSR to set both bit 11 and bit 10 to zero. Section 10.12.5, “x2APIC 
State Transitions” provides a detailed state diagram for the state transitions allowed for the local APIC.

10.12.1.1   Instructions to Access APIC Registers

In x2APIC mode, system software uses RDMSR and WRMSR to access the APIC registers. The MSR addresses for 
accessing the x2APIC registers are architecturally defined and specified in Section 10.12.1.2, “x2APIC Register 
Address Space”. Executing the RDMSR instruction with APIC register address specified in ECX returns the content 
of bits 0 through 31 of the APIC registers in EAX. Bits 32 through 63 are returned in register EDX - these bits are 
reserved if the APIC register being read is a 32-bit register. Similarly executing the WRMSR instruction with the 
APIC register address in ECX, writes bits 0 to 31 of register EAX to bits 0 to 31 of the specified APIC register. If the 
register is a 64-bit register then bits 0 to 31 of register EDX are written to bits 32 to 63 of the APIC register. The 
Interrupt Command Register is the only APIC register that is implemented as a 64-bit MSR. The semantics of 
handling reserved bits are defined in Section 10.12.1.3, “Reserved Bit Checking”.

10.12.1.2   x2APIC Register Address Space

The MSR address range 800H through BFFH is architecturally reserved and dedicated for accessing APIC registers 
in x2APIC mode. Table 10-6 lists the APIC registers that are available in x2APIC mode. When appropriate, the table 
also gives the offset at which each register is available on the page referenced by IA32_APIC_BASE[35:12] in 
xAPIC mode. 
There is a one-to-one mapping between the x2APIC MSRs and the legacy xAPIC register offsets with the following 
exceptions:

•

The Destination Format Register (DFR): The DFR, supported at offset 0E0H in xAPIC mode, is not supported in 
x2APIC mode. There is no MSR with address 80EH.

•

The Interrupt Command Register (ICR): The two 32-bit registers in xAPIC mode (at offsets 300H and 310H) are 
merged into a single 64-bit MSR in x2APIC mode (with MSR address 830H). There is no MSR with address 
831H.

•

The SELF IPI register. This register is available only in x2APIC mode at address 83FH. In xAPIC mode, there is 
no register defined at offset 3F0H.

Addresses in the range 800H–BFFH that are not listed in Table 10-6 (including 80EH and 831H) are reserved. 
Executions of RDMSR and WRMSR that attempt to access such addresses cause general-protection exceptions.
The MSR address space is compressed to allow for future growth. Every 32 bit register on a 128-bit boundary in the 
legacy MMIO space is mapped to a single MSR in the local x2APIC MSR address space. The upper 32-bits of all 
x2APIC MSRs (except for the ICR) are reserved. 

Table 10-5. x2APIC Operating Mode Configurations 

xAPIC global enable 

(IA32_APIC_BASE[11])

x2APIC enable 

(IA32_APIC_BASE[10])

Description

0

0

local APIC is disabled

0

1

Invalid

1

0

local APIC is enabled in xAPIC mode

1

1

local APIC is enabled in x2APIC mode