12-4 Vol. 3A

INTEL

®

 MMX

™

 TECHNOLOGY SYSTEM PROGRAMMING

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Execute an FSAVE, FNSAVE, or FXSAVE instruction to save the MMX state to memory. (The FXSAVE instruction 
also saves the state of the XMM and MXCSR registers.)

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Execute an FRSTOR or FXRSTOR instruction to restore the MMX state from memory. (The FXRSTOR instruction 
also restores the state of the XMM and MXCSR registers.)

The save and restore methods described above are required for operating systems (see Section 12.4, “Saving MMX 
State on Task or Context Switches”). Applications can in some cases save and restore only the MMX registers in the 
following way:

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Execute eight MOVQ instructions to save the contents of the MMX0 through MMX7 registers to memory. An 
EMMS instruction may then (optionally) be executed to clear the MMX state in the x87 FPU.

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Execute eight MOVQ instructions to read the saved contents of MMX registers from memory into the MMX0 
through MMX7 registers.

NOTE

The IA-32 architecture does not support scanning the x87 FPU tag word and then only saving valid 
entries.

12.4 

SAVING MMX STATE ON TASK OR CONTEXT SWITCHES

When switching from one task or context to another, it is often necessary to save the MMX state. As a general rule, 
if the existing task switching code for an operating system includes facilities for saving the state of the x87 FPU, 
these facilities can also be relied upon to save the MMX state, without rewriting the task switch code. This reliance 
is possible because the MMX state is aliased to the x87 FPU state (see Section 12.2, “The MMX State and MMX 
Register Aliasing”).
With the introduction of the FXSAVE and FXRSTOR instructions and of SSE/SSE2/SSE3/SSSE3 extensions, it is 
possible (and more efficient) to create state saving facilities in the operating system or executive that save the x87 
FPU/MMX/SSE/SSE2/SSE3/SSSE3 state in one operation. Section 13.4, “Designing OS Facilities for Saving x87 
FPU, SSE AND EXTENDED States on Task or Context Switches,” describes how to design such facilities. The tech-
niques describes in this section can be adapted to saving only the MMX and x87 FPU state if needed.

12.5 

EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS

MMX instructions do not generate x87 FPU floating-point exceptions, nor do they affect the processor’s status flags 
in the EFLAGS register or the x87 FPU status word. The following exceptions can be generated during the execution 
of an MMX instruction:

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Exceptions during memory accesses:
— Stack-segment fault (#SS).
— General protection (#GP).
— Page fault (#PF).
— Alignment check (#AC), if alignment checking is enabled.

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System exceptions:
— Invalid Opcode (#UD), if the EM flag in control register CR0 is set when an MMX instruction is executed (see 

Section 12.1, “Emulation of the MMX Instruction Set”).

— Device not available (#NM), if an MMX instruction is executed when the TS flag in control register CR0 is 

set. (See Section 13.4.1, “Using the TS Flag to Control the Saving of the x87 FPU and SSE State.”)

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Floating-point error (#MF). (See Section 12.5.1, “Effect of MMX Instructions on Pending x87 Floating-Point 
Exceptions.”)

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Other exceptions can occur indirectly due to the faulty execution of the exception handlers for the above 
exceptions.