9-8 Vol. 3A

PROCESSOR MANAGEMENT AND INITIALIZATION

Lists of available performance-monitoring events are given in Chapter 19, “Performance Monitoring Events”, and 
lists of available MSRs are given in Chapter 35, “Model-Specific Registers (MSRs)” The references earlier in this 
section show where the functions of the various groups of MSRs are described in this manual.

9.5 

MEMORY TYPE RANGE REGISTERS (MTRRS)

Memory type range registers (MTRRs) were introduced into the IA-32 architecture with the Pentium Pro processor. 
They allow the type of caching (or no caching) to be specified in system memory for selected physical address 
ranges. They allow memory accesses to be optimized for various types of memory such as RAM, ROM, frame buffer 
memory, and memory-mapped I/O devices.
In general, initializing the MTRRs is normally handled by the software initialization code or BIOS and is not an oper-
ating system or executive function. At the very least, all the MTRRs must be cleared to 0, which selects the 
uncached (UC) memory type. See Section 11.11, “Memory Type Range Registers (MTRRs),” for detailed informa-
tion on the MTRRs.

9.6 INITIALIZING 

SSE/SSE2/SSE3/SSSE3 

EXTENSIONS

For processors that contain SSE/SSE2/SSE3/SSSE3 extensions, steps must be taken when initializing the 
processor to allow execution of these instructions.
1. Check the CPUID feature flags for the presence of the SSE/SSE2/SSE3/SSSE3 extensions (respectively: EDX 

bits 25 and 26, ECX bit 0 and 9) and support for the FXSAVE and FXRSTOR instructions (EDX bit 24). Also check 
for support for the CLFLUSH instruction (EDX bit 19). The CPUID feature flags are loaded in the EDX and ECX 
registers when the CPUID instruction is executed with a 1 in the EAX register.

2. Set the OSFXSR flag (bit 9 in control register CR4) to indicate that the operating system supports saving and 

restoring the SSE/SSE2/SSE3/SSSE3 execution environment (XMM and MXCSR registers) with the FXSAVE and 
FXRSTOR instructions, respectively. See Section 2.5, “Control Registers,” for a description of the OSFXSR flag.

3. Set the OSXMMEXCPT flag (bit 10 in control register CR4) to indicate that the operating system supports the 

handling of SSE/SSE2/SSE3 SIMD floating-point exceptions (#XM). See Section 2.5, “Control Registers,” for a 
description of the OSXMMEXCPT flag.

4. Set the mask bits and flags in the MXCSR register according to the mode of operation desired for 

SSE/SSE2/SSE3 SIMD floating-point instructions. See “MXCSR Control and Status Register” in Chapter 10, 
“Programming with Streaming SIMD Extensions (SSE),” of the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1, for a detailed description of the bits and flags in the MXCSR register.

9.7 

SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION

Following a hardware reset (either through a power-up or the assertion of the RESET# pin) the processor is placed 
in real-address mode and begins executing software initialization code from physical address FFFFFFF0H. Software 
initialization code must first set up the necessary data structures for handling basic system functions, such as a 
real-mode IDT for handling interrupts and exceptions. If the processor is to remain in real-address mode, software 
must then load additional operating-system or executive code modules and data structures to allow reliable execu-
tion of application programs in real-address mode.
If the processor is going to operate in protected mode, software must load the necessary data structures to operate 
in protected mode and then switch to protected mode. The protected-mode data structures that must be loaded 
are described in Section 9.8, “Software Initialization for Protected-Mode Operation.”

9.7.1 

Real-Address Mode IDT

In real-address mode, the only system data structure that must be loaded into memory is the IDT (also called the 
“interrupt vector table”). By default, the address of the base of the IDT is physical address 0H. This address can be