Vol. 3A 6-27

INTERRUPT AND EXCEPTION HANDLING

Interrupt 7—Device Not Available Exception (#NM)

Exception Class

Fault.

Description

Indicates one of the following things:
The device-not-available exception is generated by either of three conditions:

•

The processor executed an x87 FPU floating-point instruction while the EM flag in control register CR0 was set 
(1). See the paragraph below for the special case of the WAIT/FWAIT instruction.

•

The processor executed a WAIT/FWAIT instruction while the MP and TS flags of register CR0 were set, 
regardless of the setting of the EM flag.

•

The processor executed an x87 FPU, MMX, or SSE/SSE2/SSE3 instruction (with the exception of MOVNTI, 
PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, and CLFLUSH) while the TS flag in control register CR0 was set 
and the EM flag is clear.

The EM flag is set when the processor does not have an internal x87 FPU floating-point unit. A device-not-available 
exception is then generated each time an x87 FPU floating-point instruction is encountered, allowing an exception 
handler to call floating-point instruction emulation routines.
The TS flag indicates that a context switch (task switch) has occurred since the last time an x87 floating-point, 
MMX, or SSE/SSE2/SSE3 instruction was executed; but that the context of the x87 FPU, XMM, and MXCSR registers 
were not saved. When the TS flag is set and the EM flag is clear, the processor generates a device-not-available 
exception each time an x87 floating-point, MMX, or SSE/SSE2/SSE3 instruction is encountered (with the exception 
of the instructions listed above). The exception handler can then save the context of the x87 FPU, XMM, and MXCSR 
registers before it executes the instruction. See Section 2.5, “Control Registers,” for more information about the TS 
flag.
The MP flag in control register CR0 is used along with the TS flag to determine if WAIT or FWAIT instructions should 
generate a device-not-available exception. It extends the function of the TS flag to the WAIT and FWAIT instruc-
tions, giving the exception handler an opportunity to save the context of the x87 FPU before the WAIT or FWAIT 
instruction is executed. The MP flag is provided primarily for use with the Intel 286 and Intel386 DX processors. For 
programs running on the Pentium 4, Intel Xeon, P6 family, Pentium, or Intel486 DX processors, or the Intel 487 SX 
coprocessors, the MP flag should always be set; for programs running on the Intel486 SX processor, the MP flag 
should be clear. 

Exception Error Code

None.

Saved Instruction Pointer

The saved contents of CS and EIP registers point to the floating-point instruction or the WAIT/FWAIT instruction 
that generated the exception.

Program State Change

A program-state change does not accompany a device-not-available fault, because the instruction that generated 
the exception is not executed.
If the EM flag is set, the exception handler can then read the floating-point instruction pointed to by the EIP and 
call the appropriate emulation routine.
If the MP and TS flags are set or the TS flag alone is set, the exception handler can save the context of the x87 FPU, 
clear the TS flag, and continue execution at the interrupted floating-point or WAIT/FWAIT instruction.