9-36 Vol. 3A

PROCESSOR MANAGEMENT AND INITIALIZATION

and platform ID bits of the processor that it is running on against the available headers before loading a 
particular update. The number of updates is only limited by available BIOS space.

•

A loader can load the update and test the processor to determine if the update was loaded correctly. See 
Section 9.11.7, “Update Signature and Verification.”

•

A loader can verify the integrity of the update data by performing a checksum on the double words of the 
update summing to zero. See Section 9.11.5, “Microcode Update Checksum.”

•

A loader can provide power-on messages indicating successful loading of an update.

9.11.7 

Update Signature and Verification

The P6 family and later processors provide capabilities to verify the authenticity of a particular update and to iden-
tify the current update revision. This section describes the model-specific extensions of processors that support 
this feature. The update verification method below assumes that the BIOS will only verify an update that is more 
recent than the revision currently loaded in the processor.
CPUID returns a value in a model specific register in addition to its usual register return values. The semantics of 
CPUID cause it to deposit an update ID value in the 64-bit model-specific register at address 08BH 
(IA32_BIOS_SIGN_ID). If no update is present in the processor, the value in the MSR remains unmodified. The 
BIOS must pre-load a zero into the MSR before executing CPUID. If a read of the MSR at 8BH still returns zero after 
executing CPUID, this indicates that no update is present.
The update ID value returned in the EDX register after RDMSR executes indicates the revision of the update loaded 
in the processor. This value, in combination with the CPUID value returned in the EAX register, uniquely identifies a 
particular update. The signature ID can be directly compared with the update revision field in a microcode update 
header for verification of a correct load. No consecutive updates released for a given stepping of a processor may 
share the same signature. The processor signature returned by CPUID differentiates updates for different step-
pings.

9.11.7.1   Determining the Signature

An update that is successfully loaded into the processor provides a signature that matches the update revision of 
the currently functioning revision. This signature is available any time after the actual update has been loaded. 
Requesting the signature does not have a negative impact upon a loaded update.  
The procedure for determining this signature shown in Example 9-9.

Example 9-9.  Assembly Code to Retrieve the Update Revision

MOV

ECX, 08BH

;IA32_BIOS_SIGN_ID

XOR

EAX, EAX

;clear EAX

XOR

EDX, EDX

;clear EDX

WRMSR

;Load 0 to MSR at 8BH

MOV

EAX, 1

cpuid

MOV

ECX, 08BH

;IA32_BIOS_SIGN_ID

rdmsr

;Read Model Specific Register

If there is an update active in the processor, its revision is returned in the EDX register after the RDMSR instruction 
executes.

IA32_BIOS_SIGN_ID

Microcode Update Signature Register 

MSR Address:

08BH Accessed as a Qword

Default Value:

XXXX XXXX XXXX XXXXh

Access:

Read/Write

The IA32_BIOS_SIGN_ID register is used to report the microcode update signature when CPUID executes. The 
signature is returned in the upper DWORD (Table 9-12).