6-4 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

6.3.3 Software-Generated 

Interrupts

The INT n instruction permits interrupts to be generated from within software by supplying an interrupt vector 
number as an operand. For example, the INT 35 instruction forces an implicit call to the interrupt handler for inter-
rupt 35. 
Any of the interrupt vectors from 0 to 255 can be used as a parameter in this instruction. If the processor’s 
predefined NMI vector is used, however, the response of the processor will not be the same as it would be from an 
NMI interrupt generated in the normal manner. If vector number 2 (the NMI vector) is used in this instruction, the 
NMI interrupt handler is called, but the processor’s NMI-handling hardware is not activated. 
Interrupts generated in software with the INT n instruction cannot be masked by the IF flag in the EFLAGS register.

6.4 SOURCES 

OF 

EXCEPTIONS

The processor receives exceptions from three sources:

•

Processor-detected program-error exceptions.

•

Software-generated exceptions.

•

Machine-check exceptions.

6.4.1 Program-Error 

Exceptions

The processor generates one or more exceptions when it detects program errors during the execution in an appli-
cation program or the operating system or executive. Intel 64 and IA-32 architectures define a vector number for 
each processor-detectable exception. Exceptions are classified as faults, traps, and aborts (see Section 6.5, 
“Exception Classifications”).

6.4.2 Software-Generated 

Exceptions

The INTO, INT 3, and BOUND instructions permit exceptions to be generated in software. These instructions allow 
checks for exception conditions to be performed at points in the instruction stream. For example, INT 3 causes a 
breakpoint exception to be generated.
The INT n instruction can be used to emulate exceptions in software; but there is a limitation. If INT n provides a 
vector for one of the architecturally-defined exceptions, the processor generates an interrupt to the correct vector 
(to access the exception handler) but does not push an error code on the stack. This is true even if the associated 
hardware-generated exception normally produces an error code. The exception handler will still attempt to pop an 
error code from the stack while handling the exception. Because no error code was pushed, the handler will pop off 
and discard the EIP instead (in place of the missing error code). This sends the return to the wrong location.

6.4.3 Machine-Check 

Exceptions

The P6 family and Pentium processors provide both internal and external machine-check mechanisms for checking 
the operation of the internal chip hardware and bus transactions. These mechanisms are implementation depen-
dent. When a machine-check error is detected, the processor signals a machine-check exception (vector 18) and 
returns an error code. 
See Chapter 6, “Interrupt 18—Machine-Check Exception (#MC)” and Chapter 15, “Machine-Check Architecture,” 
for more information about the machine-check mechanism.

6.5 EXCEPTION 

CLASSIFICATIONS

Exceptions are classified as faults, traps, or aborts depending on the way they are reported and whether the 
instruction that caused the exception can be restarted without loss of program or task continuity.