Vol. 3C 29-1

CHAPTER 29

APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS

The VMCS includes controls that enable the virtualization of interrupts and the Advanced Programmable Interrupt 
Controller (APIC).
When these controls are used, the processor will emulate many accesses to the APIC, track the state of the virtual 
APIC, and deliver virtual interrupts — all in VMX non-root operation with out a VM exit.

1

The processor tracks the state of the virtual APIC using a virtual-APIC page identified by the virtual-machine 
monitor (VMM). Section 29.1 discusses the virtual-APIC page and how the processor uses it to track the state of the 
virtual APIC.
The following are the VM-execution controls relevant to APIC virtualization and virtual interrupts (see Section 24.6 
for information about the locations of these controls):

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Virtual-interrupt delivery. This controls enables the evaluation and delivery of pending virtual interrupts 
(Section 29.2). It also enables the emulation of writes (memory-mapped or MSR-based, as enabled) to the 
APIC registers that control interrupt prioritization.

•

Use TPR shadow. This control enables emulation of accesses to the APIC’s task-priority register (TPR) via CR8 
(Section 29.3) and, if enabled, via the memory-mapped or MSR-based interfaces.

•

Virtualize APIC accesses. This control enables virtualization of memory-mapped accesses to the APIC 
(Section 29.4) by causing VM exits on accesses to a VMM-specified APIC-access page. Some of the other 
controls, if set, may cause some of these accesses to be emulated rather than causing VM exits.

•

Virtualize x2APIC mode. This control enables virtualization of MSR-based accesses to the APIC (Section 
29.5).

•

APIC-register virtualization. This control allows memory-mapped and MSR-based reads of most APIC 
registers (as enabled) by satisfying them from the virtual-APIC page. It directs memory-mapped writes to the 
APIC-access page to the virtual-APIC page, following them by VM exits for VMM emulation.

•

Process posted interrupts. This control allows software to post virtual interrupts in a data structure and send 
a notification to another logical processor; upon receipt of the notification, the target processor will process the 
posted interrupts by copying them into the virtual-APIC page (Section 29.6).

“Virtualize APIC accesses”, “virtualize x2APIC mode”, “virtual-interrupt delivery”, and “APIC-register virtualization” 
are all secondary processor-based VM-execution controls. If bit 31 of the primary processor-based VM-execution 
controls is 0, the processor operates as if these controls were all 0. See Section 24.6.2.

29.1 VIRTUAL 

APIC 

STATE

The virtual-APIC page is a 4-KByte region of memory that the processor uses to virtualize certain accesses to 
APIC registers and to manage virtual interrupts. The physical address of the virtual-APIC page is the virtual-APIC 
address, a 64-bit VM-execution control field in the VMCS (see Section 24.6.8).
Depending on the settings of certain VM-execution controls, the processor may virtualize certain fields on the 
virtual-APIC page with functionality analogous to that performed by the local APIC. Section 29.1.1 identifies and 
defines these fields. Section 29.1.2, Section 29.1.3, Section 29.1.4, and Section 29.1.5 detail the actions taken to 
virtualize updates to some of these fields.

29.1.1 

Virtualized APIC Registers

Depending on the setting of certain VM-execution controls, a logical processor may virtualize certain accesses to 
APIC registers using the following fields on the virtual-APIC page:

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Virtual task-priority register (VTPR): the 32-bit field located at offset 080H on the virtual-APIC page.

1. In most cases, it is not necessary for a virtual-machine monitor (VMM) to inject virtual interrupts as part of VM entry.