32-4 Vol. 3C

VIRTUALIZATION OF SYSTEM RESOURCES

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Suppose the guest page-table hierarchy allows more access than active hierarchy (for example: there is a 
translation for a linear address in the guest hierarchy but not in the active hierarchy); this is analogous to a 
situation in which the TLB allows less access than the page-table hierarchy. If an access occurs that would be 
allowed by the guest hierarchy but not the active one, a page fault occurs; this is analogous to a TLB miss. The 
VMM gains control (as it handles all page faults) and can update the active page-table hierarchy appropriately; 
this corresponds to a TLB fill.

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Suppose the guest page-table hierarchy allows less access than the active hierarchy; this is analogous to a 
situation in which the TLB allows more access than the page-table hierarchy. This situation can occur only if the 
guest operating system has modified a page-table entry to reduce access (for example: by marking it not-
present). Because the older, more permissive translation may have been cached in the TLB, the processor is 
architecturally permitted to use the older translation and allow more access. Thus, the VMM may (through the 
active page-table hierarchy) also allow greater access. For the new, less permissive translation to take effect, 
guest software should flush any older translations from the TLB either by executing INVLPG or by loading CR3. 
Because both these operations will cause a trap to the VMM, the VMM will gain control and can remove from the 
active page-table hierarchy the translations indicated by guest software (the translation of a specific linear 
address for INVLPG or all translations for a load of CR3).

As noted previously, the processor reads the page-table hierarchy to cache translations in the TLB. It also writes to 
the hierarchy to main the accessed (A) and dirty (D) bits in the PDEs and PTEs. The virtual TLB emulates this 
behavior as follows:

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When a page is accessed by guest software, the A bit in the corresponding PTE (or PDE for a 4-MByte page) in 
the active page-table hierarchy will be set by the processor (the same is true for PDEs when active page tables 
are accessed by the processor). For guest software to operate properly, the VMM should update the A bit in the 
guest entry at this time. It can do this reliably if it keeps the active PTE (or PDE) marked not-present until it has 
set the A bit in the guest entry.

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When a page is written by guest software, the D bit in the corresponding PTE (or PDE for a 4-MByte page) in 
the active page-table hierarchy will be set by the processor. For guest software to operate properly, the VMM 
should update the D bit in the guest entry at this time. It can do this reliably if it keeps the active PTE (or PDE) 
marked read-only until it has set the D bit in the guest entry. This solution is valid for guest software running at 
privilege level 3; support for more privileged guest software is described in Section 32.3.5.

32.3.5 

Details of Virtual TLB Operation

This section describes in more detail how a VMM could support a virtual TLB. It explains how an active page-table 
hierarchy is initialized and how it is maintained in response to page faults, uses of INVLPG, and accesses to CR3. 
The mechanisms described here are the minimum necessary. They may not result in the best performance.