Vol. 3B 22-19

ARCHITECTURE COMPATIBILITY

22.22.4  Changes in Segment Descriptor Loads

On the Intel386 processor, loading a segment descriptor always causes a locked read and write to set the accessed 
bit of the descriptor. On the P6 family, Pentium, and Intel486 processors, the locked read and write occur only if the 
bit is not already set.

22.23 DEBUG 

FACILITIES

The P6 family and Pentium processors include extensions to the Intel486 processor debugging support for break-
points. To use the new breakpoint features, it is necessary to set the DE flag in control register CR4.

22.23.1  Differences in Debug Register DR6

It is not possible to write a 1 to reserved bit 12 in debug status register DR6 on the P6 family and Pentium proces-
sors; however, it is possible to write a 1 in this bit on the Intel486 processor. See Table 9-1 for the different setting 
of this register following a power-up or hardware reset.

22.23.2  Differences in Debug Register DR7

The P6 family and Pentium processors determines the type of breakpoint access by the R/W0 through R/W3 fields 
in debug control register DR7 as follows: 
00

Break on instruction execution only.

01

Break on data writes only.

10

Undefined if the DE flag in control register CR4 is cleared; break on I/O reads or writes but not instruction 
fetches if the DE flag in control register CR4 is set.

11

Break on data reads or writes but not instruction fetches.

On the P6 family and Pentium processors, reserved bits 11, 12, 14 and 15 are hard-wired to 0. On the Intel486 
processor, however, bit 12 can be set. See Table 9-1 for the different settings of this register following a power-up 
or hardware reset.

22.23.3  Debug Registers DR4 and DR5

Although the DR4 and DR5 registers are documented as reserved, previous generations of processors aliased 
references to these registers to debug registers DR6 and DR7, respectively. When debug extensions are not 
enabled (the DE flag in control register CR4 is cleared), the P6 family and Pentium processors remain compatible 
with existing software by allowing these aliased references. When debug extensions are enabled (the DE flag is 
set), attempts to reference registers DR4 or DR5 will result in an invalid-opcode exception (#UD).

22.24 RECOGNITION 

OF 

BREAKPOINTS

For the Pentium processor, it is recommended that debuggers execute the LGDT instruction before returning to the 
program being debugged to ensure that breakpoints are detected. This operation does not need to be performed 
on the P6 family, Intel486, or Intel386 processors. 
The implementation of test registers on the Intel486 processor used for testing the cache and TLB has been rede-
signed using MSRs on the P6 family and Pentium processors. (Note that MSRs used for this function are different 
on the P6 family and Pentium processors.) The MOV to and from test register instructions generate invalid-opcode 
exceptions (#UD) on the P6 family processors.