26-16 Vol. 3C

VM ENTRIES

26.3.2.2   Loading Guest Segment Registers and Descriptor-Table Registers

For each of CS, SS, DS, ES, FS, GS, TR, and LDTR, fields are loaded from the guest-state area as follows:

•

The unusable bit is loaded from the access-rights field. This bit can never be set for TR (see Section 26.3.1.2). 
If it is set for one of the other registers, the following apply:
— For each of CS, SS, DS, ES, FS, and GS, uses of the segment cause faults (general-protection exception or 

stack-fault exception) outside 64-bit mode, just as they would had the segment been loaded using a null 
selector. This bit does not cause accesses to fault in 64-bit mode.

— If this bit is set for LDTR, uses of LDTR cause general-protection exceptions in all modes, just as they would 

had LDTR been loaded using a null selector.

If this bit is clear for any of CS, SS, DS, ES, FS, GS, TR, and LDTR, a null selector value does not cause a fault
(general-protection exception or stack-fault exception).

•

TR. The selector, base, limit, and access-rights fields are loaded.

•

CS.
— The following fields are always loaded: selector, base address, limit, and (from the access-rights field) the 

L, D, and G bits.

— For the other fields, the unusable bit of the access-rights field is consulted:

•

If the unusable bit is 0, all of the access-rights field is loaded.

•

If the unusable bit is 1, the remainder of CS access rights are undefined after VM entry.

•

SS, DS, ES, FS, GS, and LDTR.
— The selector fields are loaded.
— For the other fields, the unusable bit of the corresponding access-rights field is consulted:

•

If the unusable bit is 0, the base-address, limit, and access-rights fields are loaded.

•

If the unusable bit is 1, the base address, the segment limit, and the remainder of the access rights are 

undefined after VM entry with the following exceptions:

— Bits 3:0 of the base address for SS are cleared to 0.
— SS.DPL  is  always  loaded  from  the  SS  access-rights field. This will be the current privilege level

(CPL) after the VM entry completes.

— SS.B is always set to 1.
— The base addresses for FS and GS are loaded from the corresponding fields in the VMCS. On

processors that support Intel 64 architecture, the values loaded for base addresses for FS and GS
are also manifest in the FS.base and GS.base MSRs.

— On processors that support Intel 64 architecture, the base address for LDTR is set to an undefined

but canonical value.

— On processors that support Intel 64 architecture, bits 63:32 of the base addresses for SS, DS, and

ES are cleared to 0.

GDTR and IDTR are loaded using the base and limit fields.

26.3.2.3   Loading Guest RIP, RSP, and RFLAGS

RSP, RIP, and RFLAGS are loaded from the RSP field, the RIP field, and the RFLAGS field, respectively. The following 
items regard the upper 32 bits of these fields on VM entries that are not to 64-bit mode:

•

Bits 63:32 of RSP are undefined outside 64-bit mode. Thus, a logical processor may ignore the contents of 
bits 63:32 of the RSP field on VM entries that are not to 64-bit mode.

•

As noted in Section 26.3.1.4, bits 63:32 of the RIP and RFLAGS fields must be 0 on VM entries that are not to 
64-bit mode.