Vol. 3A 10-29

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

The processor-priority class is a value in the range 0–15 that is maintained in bits 7:4 of the processor-priority 
register (PPR); see Figure 10-19. The PPR is a read-only register. The processor-priority class represents the 
current priority at which the processor is executing.

The value of the PPR is based on the value of TPR and the value ISRV; ISRV is the vector number of the highest 
priority bit that is set in the ISR or 00H if no bit is set in the ISR. (See Section 10.8.4 for more details on the ISR.) 
The value of PPR is determined as follows:

•

PPR[7:4] (the processor-priority class) the maximum of TPR[7:4] (the task- priority class) and ISRV[7:4] (the 
priority of the highest priority interrupt in service).

•

PPR[3:0] (the processor-priority sub-class) is determined as follows:
— If TPR[7:4] > ISRV[7:4], PPR[3:0] is TPR[3:0] (the task-priority sub-class).
— If TPR[7:4] < ISRV[7:4], PPR[3:0] is 0.
— If TPR[7:4] = ISRV[7:4], PPR[3:0] may be either TPR[3:0] or 0. The actual behavior is model-specific.

The processor-priority class determines the priority threshold for interrupting the processor. The processor will 
deliver only those interrupts that have an interrupt-priority class higher than the processor-priority class in the 
PPR. If the processor-priority class is 0, the PPR does not inhibit the delivery any interrupt; if it is 15, the processor 
inhibits the delivery of all interrupts. (The processor-priority mechanism does not affect the delivery of interrupts 
with the NMI, SMI, INIT, ExtINT, INIT-deassert, and start-up delivery modes.)
The processor does not use the processor-priority sub-class to determine which interrupts to delivery and which to 
inhibit. (The processor uses the processor-priority sub-class only to satisfy reads of the PPR.)

10.8.4 

Interrupt Acceptance for Fixed Interrupts

The local APIC queues the fixed interrupts that it accepts in one of two interrupt pending registers: the interrupt 
request register (IRR) or in-service register (ISR). These two 256-bit read-only registers are shown in 
Figure 10-20. The 256 bits in these registers represent the 256 possible vectors; vectors 0 through 15 are reserved 
by the APIC (see also: Section 10.5.2, “Valid Interrupt Vectors”).

NOTE

All interrupts with an NMI, SMI, INIT, ExtINT, start-up, or INIT-deassert delivery mode bypass the 
IRR and ISR registers and are sent directly to the processor core for servicing.

The IRR contains the active interrupt requests that have been accepted, but not yet dispatched to the processor for 
servicing. When the local APIC accepts an interrupt, it sets the bit in the IRR that corresponds the vector of the 
accepted interrupt. When the processor core is ready to handle the next interrupt, the local APIC clears the highest 
priority IRR bit that is set and sets the corresponding ISR bit. The vector for the highest priority bit set in the ISR 
is then dispatched to the processor core for servicing. 
While the processor is servicing the highest priority interrupt, the local APIC can send additional fixed interrupts by 
setting bits in the IRR. When the interrupt service routine issues a write to the EOI register (see Section 10.8.5, 
“Signaling Interrupt Servicing Completion”), the local APIC responds by clearing the highest priority ISR bit that is 
set. It then repeats the process of clearing the highest priority bit in the IRR and setting the corresponding bit in 
the ISR. The processor core then begins executing the service routing for the highest priority bit set in the ISR.

 

Figure 10-19.  Processor-Priority Register (PPR)

31

0

7

8

Reserved

Address: FEE0 00A0H
Value after reset: 0H

Processor-Priority Sub-Class

Processor-Priority Class

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