4-36 Vol. 3A

PAGING

If CR4.PCIDE = 0, a logical processor does not cache information for any PCID other than 000H. This is because 
(1) if CR4.PCIDE = 0, the logical processor will associate any newly cached information with the current PCID, 
000H; and (2) if MOV to CR4 clears CR4.PCIDE, all cached information is invalidated (see Section 4.10.4.1).

NOTE

In revisions of this manual that were produced when no processors allowed CR4.PCIDE to be set to 
1, 

Section 4.10 discussed the caching of translation information without any reference to PCIDs. 

While the section now refers to PCIDs in its specification of this caching, this documentation change 
is not intended to imply any change to the behavior of processors that do not allow CR4.PCIDE to 
be set to 1.

4.10.2 

Translation Lookaside Buffers (TLBs)

A processor may cache information about the translation of linear addresses in translation lookaside buffers (TLBs). 
In general, TLBs contain entries that map page numbers to page frames; these terms are defined in Section 
4.10.2.1. Section 4.10.2.2 describes how information may be cached in TLBs, and Section 4.10.2.3 gives details of 
TLB usage. Section 4.10.2.4 explains the global-page feature, which allows software to indicate that certain trans-
lations should receive special treatment when cached in the TLBs.

4.10.2.1   Page Numbers, Page Frames, and Page Offsets

Section 4.3, Section 4.4.2, and Section 4.5 give details of how the different paging modes translate linear 
addresses to physical addresses. Specifically, the upper bits of a linear address (called the page number) deter-
mine the upper bits of the physical address (called the page frame); the lower bits of the linear address (called the 
page offset) determine the lower bits of the physical address. The boundary between the page number and the 
page offset is determined by the page size. Specifically:

•

32-bit paging:
— If the translation does not use a PTE (because CR4.PSE = 1 and the PS flag is 1 in the PDE used), the page 

size is 4 MBytes and the page number comprises bits 31:22 of the linear address.

— If the translation does use a PTE, the page size is 4 KBytes and the page number comprises bits 31:12 of 

the linear address.

•

PAE paging:
— If the translation does not use a PTE (because the PS flag is 1 in the PDE used), the page size is 2 MBytes 

and the page number comprises bits 31:21 of the linear address.

— If the translation does uses a PTE, the page size is 4 KBytes and the page number comprises bits 31:12 of 

the linear address.

•

IA-32e paging:
— If the translation does not use a PDE (because the PS flag is 1 in the PDPTE used), the page size is 1 GByte 

and the page number comprises bits 47:30 of the linear address.

— If the translation does use a PDE but does not uses a PTE (because the PS flag is 1 in the PDE used), the 

page size is 2 MBytes and the page number comprises bits 47:21 of the linear address.

— If the translation does use a PTE, the page size is 4 KBytes and the page number comprises bits 47:12 of 

the linear address.

4.10.2.2   Caching Translations in TLBs

The processor may accelerate the paging process by caching individual translations in translation lookaside 
buffers (TLBs). Each entry in a TLB is an individual translation. Each translation is referenced by a page number. 
It contains the following information from the paging-structure entries used to translate linear addresses with the 
page number:

•

The physical address corresponding to the page number (the page frame).