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17-10 Vol. 3B


ation clears the TF flag. After saving the return address or switching tasks, the external interrupt input is examined 
before the first instruction of the single-step handler executes. If the external interrupt is still pending, then it is 
serviced. The external interrupt handler does not run in single-step mode. To single step an interrupt handler, 
single step an INT n instruction that calls the interrupt handler.   Task-Switch Exception Condition

The processor generates a debug exception after a task switch if the T flag of the new task's TSS is set. This excep-
tion is generated after program control has passed to the new task, and prior to the execution of the first instruc-
tion of that task. The exception handler can detect this condition by examining the BT flag of the DR6 register.
If entry 1 (#DB) in the IDT is a task gate, the T bit of the corresponding TSS should not be set. Failure to observe 
this rule will put the processor in a loop.


Breakpoint Exception (#BP)—Interrupt Vector 3

The breakpoint exception (interrupt 3) is caused by execution of an INT 3 instruction. See Chapter 6, “Interrupt 
3—Breakpoint Exception (#BP).” 
Debuggers use break exceptions in the same way that they use the breakpoint 
registers; that is, as a mechanism for suspending program execution to examine registers and memory locations. 
With earlier IA-32 processors, breakpoint exceptions are used extensively for setting instruction breakpoints.
With the Intel386 and later IA-32 processors, it is more convenient to set breakpoints with the breakpoint-address 
registers (DR0 through DR3). However, the breakpoint exception still is useful for breakpointing debuggers, 
because a breakpoint exception can call a separate exception handler. The breakpoint exception is also useful when 
it is necessary to set more breakpoints than there are debug registers or when breakpoints are being placed in the 
source code of a program under development.


Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory 


Chapter 16, “Programming with Intel® Transactional Synchronization Extensions,” of Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1
 describes Restricted Transactional Memory (RTM). This is an 
instruction-set interface that allows software to identify transactional regions (or critical sections) using the 
XBEGIN and XEND instructions.
Execution of an RTM transactional region begins with an XBEGIN instruction. If execution of the region successfully 
reaches an XEND instruction, the processor ensures that all memory operations performed within the region 
appear to have occurred instantaneously when viewed from other logical processors. Execution of an RTM transac-
tion region does not succeed if the processor cannot commit the updates atomically. When this happens, the 
processor rolls back the execution, a process referred to as a transactional abort. In this case, the processor 
discards all updates performed in the region, restores architectural state to appear as if the execution had not 
occurred, and resumes execution at a fallback instruction address that was specified with the XBEGIN instruction.
If debug exception (#DB) or breakpoint exception (#BP) occurs within an RTM transaction region, a transactional 
abort occurs, the processor sets EAX[4], and no exception is delivered.
Software can enable advanced debugging of RTM transactional regions by setting DR7.RTM[bit 11] and 
IA32_DEBUGCTL.RTM[bit 15]. If these bits are both set, the transactional abort caused by a #DB or #BP within an 
RTM transaction region does not resume execution at the fallback instruction address specified with the XBEGIN 
instruction that begin the region. Instead, execution is resumed at that XBEGIN instruction, and a #DB is delivered. 
(A #DB is delivered even if the transactional abort was caused by a #BP.) Such a #DB will clear DR6.RTM[bit 16] 
(all other debug exceptions set DR6[16]).



P6 family processors introduced the ability to set breakpoints on taken branches, interrupts, and exceptions, and 
to single-step from one branch to the next. This capability has been modified and extended in the Pentium 4, Intel