13-2 Vol. 3A

SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES

Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2)” and Chapter 12, “Programming with SSE3, 
SSSE3 and SSE4,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, provide 
details on SSE instruction set.

13.1.1 

Adding Support to an Operating System for SSE Extensions

The following guidelines describe functions that an operating system or executive must perform to support SSE 
extensions:
1. Check that the processor supports the SSE extensions.
2. Check that the processor supports the FXSAVE and FXRSTOR instructions or the XSAVE feature set.
3. Provide an initialization for the SSE states.
4. Provide support for the FXSAVE and FXRSTOR instructions or the XSAVE feature set.
5. Provide support (if necessary) in non-numeric exception handlers for exceptions generated by the SSE instruc-

tions.

6. Provide an exception handler for the SIMD floating-point exception (#XM).
The following sections describe how to implement each of these guidelines.

13.1.2 

Checking for CPU Support

If the processor attempts to execute an unsupported SSE instruction, the processor generates an invalid-opcode 
exception (#UD). Before an operating system or executive attempts to use SSE extensions, it should check that 
support is present by confirming the following bit values returned by the CPUID instruction:

•

CPUID.1:EDX.SSE[bit 25] = 1

•

CPUID.1:EDX.SSE2[bit 26] = 1

•

CPUID.1:ECX.SSE3[bit 0] = 1

•

CPUID.1:ECX.SSSE3[bit 9] = 1

•

CPUID.1:ECX.SSE4_1[bit 19] = 1

•

CPUID.1:ECX.SSE4_2[bit 20] = 1

(To use POPCNT instruction, software must check CPUID.1:ECX.POPCNT[bit 23] = 1.)
Separate checks must be made to ensure that the processor supports either FXSAVE and FXRSTOR or the XSAVE 
feature set. See Section 10.5 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 and 
Chapter 13 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, respectively.

13.1.3 

Initialization of the SSE Extensions

The operating system or executive should carry out the following steps to set up SSE extensions for use by appli-
cation programs:
1. Set CR4.OSFXSR[bit 9] = 1. Setting this flag implies that the operating system provides facilities for saving 

and restoring SSE state using FXSAVE and FXRSTOR instructions. These instructions may be used to save the 
SSE state during task switches and when invoking the SIMD floating-point exception (#XM) handler (see 
Section 13.1.5, “Providing a Handler for the SIMD Floating-Point Exception (#XM)”). 
If the processor does not support the FXSAVE and FXRSTOR instructions, attempting to set the OSFXSR flag 
causes a general-protection exception (#GP) to be generated.