29-8 Vol. 3C
APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS
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If the “APIC-register virtualization” and “virtual-interrupt delivery” VM-execution controls are both 0, a write
access is virtualized if its page offset is 080H; otherwise, the access causes an APIC-access VM exit.
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If the “APIC-register virtualization” VM-execution control is 0 and the “virtual-interrupt delivery” VM-execution
control is 1, a write access is virtualized if its page offset is 080H (task priority), 0B0H (end of interrupt), and
300H (interrupt command — low); otherwise, the access causes an APIC-access VM exit.
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If “APIC-register virtualization is 1, a write access is virtualized if it is entirely within one the following ranges of
offsets:
— 020H–023H (local APIC ID);
— 080H–083H (task priority);
— 0B0H–0B3H (end of interrupt);
— 0D0H–0D3H (logical destination);
— 0E0H–0E3H (destination format);
— 0F0H–0F3H (spurious-interrupt vector);
— 280H–283H (error status);
— 300H–303H or 310H–313H (interrupt command);
— 320H–323H, 330H–333H, 340H–343H, 350H–353H, 360H–363H, or 370H–373H (LVT entries);
— 380H–383H (initial count); or
— 3E0H–3E3H (divide configuration).
In all other cases, the access causes an APIC-access VM exit.
The processor virtualizes a write access to the APIC-access page by writing data to the corresponding page offset
on the virtual-APIC page.
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Following this, the processor performs certain actions after completion of the operation
of which the access was a part.
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APIC-write emulation is described in Section 29.4.3.2.
29.4.3.2 APIC-Write Emulation
If the processor virtualizes a write access to the APIC-access page, it performs additional actions after completion
of an operation of which the access was a part. These actions are called APIC-write emulation.
The details of APIC-write emulation depend upon the page offset of the virtualized write access:
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080H (task priority). The processor clears bytes 3:1 of VTPR and then causes TPR virtualization (Section
29.1.2).
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0B0H (end of interrupt). If the “virtual-interrupt delivery” VM-execution control is 1, the processor clears VEOI
and then causes EOI virtualization (Section 29.1.4); otherwise, the processor causes an APIC-write VM exit
(Section 29.4.3.3).
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300H (interrupt command — low). If the “virtual-interrupt delivery” VM-execution control is 1, the processor
checks the value of VICR_LO to determine whether the following are all true:
— Reserved bits (31:20, 17:16, 13) and bit 12 (delivery status) are all 0.
— Bits 19:18 (destination shorthand) are 01B (self).
— Bit 15 (trigger mode) is 0 (edge).
— Bits 10:8 (delivery mode) are 000B (fixed).
— Bits 7:4 (the upper half of the vector) are not 0000B.
5. The memory type used for accesses that write to the virtual-APIC page is reported in bits 53:50 of the IA32_VMX_BASIC MSR (see
6. Recall that, for the purposes of this discussion, an operation is an iteration of a REP-prefixed string instruction, an execution of any
other instruction, or delivery of an event through the IDT.
7. For any operation, there can be only one page offset for which a write access was virtualized. This is because a write access is not
virtualized if the processor has already virtualized a write access for the same operation with a different page offset.