Vol. 3A 2-23

SYSTEM ARCHITECTURE OVERVIEW

The LAR (load access rights) instruction verifies the accessibility of a specified segment and loads access rights 
information from the segment’s segment descriptor into a general-purpose register. Software can then examine 
the access rights to determine if the segment type is compatible with its intended use. See Section 5.10.1, 
“Checking Access Rights (LAR Instruction)” for a detailed explanation of the function and use of this instruction.
The LSL (load segment limit) instruction verifies the accessibility of a specified segment and loads the segment 
limit from the segment’s segment descriptor into a general-purpose register. Software can then compare the 
segment limit with an offset into the segment to determine whether the offset lies within the segment. See Section 
5.10.3, “Checking That the Pointer Offset Is Within Limits (LSL Instruction)” for a detailed explanation of the func-
tion and use of this instruction.
The VERR (verify for reading) and VERW (verify for writing) instructions verify if a selected segment is readable or 
writable, respectively, at a given CPL. See Section 5.10.2, “Checking Read/Write Rights (VERR and VERW Instruc-
tions)” for a detailed explanation of the function and use of these instructions.

2.8.3 

Loading and Storing Debug Registers

Internal debugging facilities in the processor are controlled by a set of 8 debug registers (DR0-DR7). The MOV 
instruction allows setup data to be loaded to and stored from these registers.
On processors that support Intel 64 architecture, debug registers DR0-DR7 are 64 bits. In 32-bit modes and 
compatibility mode, writes to a debug register fill the upper 32 bits with zeros. Reads return the lower 32 bits. In 
64-bit mode, the upper 32 bits of DR6-DR7 are reserved and must be written with zeros. Writing one to any of the 
upper 32 bits causes an exception, #GP(0).
In 64-bit mode, MOV DRn instructions read or write all 64 bits of a debug register (operand-size prefixes are 
ignored). All 64 bits of DR0-DR3 are writable by software. However, MOV DRn instructions do not check that 
addresses written to DR0-DR3 are in the limits of the implementation. Address matching is supported only on valid 
addresses generated by the processor implementation.

2.8.4 

Invalidating Caches and TLBs

The processor provides several instructions for use in explicitly invalidating its caches and TLB entries. The INVD 
(invalidate cache with no writeback) instruction invalidates all data and instruction entries in the internal caches 
and sends a signal to the external caches indicating that they should also be invalidated.
The WBINVD (invalidate cache with writeback) instruction performs the same function as the INVD instruction, 
except that it writes back modified lines in its internal caches to memory before it invalidates the caches. After 
invalidating the caches local to the executing logical processor or processor core, WBINVD signals caches higher in 
the cache hierarchy (caches shared with the invalidating logical processor or core) to write back any data they have 
in modified state at the time of instruction execution and to invalidate their contents. 
Note, non-shared caches may not be written back nor invalidated. In Figure 2-10 below, if code executing on either 
LP0 or LP1 were to execute a WBINVD, the shared L1 and L2 for LP0/LP1 will be written back and invalidated as will 
the shared L3. However, the L1 and L2 caches not shared with LP0 and LP1 will not be written back nor invalidated.