Vol. 3B 17-25

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

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After reading the data in the appropriate buffer, up to but not including the current index into the buffer, the ISR 
must reset the buffer index to the beginning of the buffer. Otherwise, everything up to the index will look like 
new entries upon the next invocation of the ISR.

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The ISR must clear the mask bit in the performance counter LVT entry.

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The ISR must re-enable the counters to count via IA32_PERF_GLOBAL_CTRL/IA32_PERF_GLOBAL_OVF_CTRL 
if it is servicing an overflow PMI due to PEBS (or via CCCR's ENABLE bit on processor based on Intel NetBurst 
microarchitecture).

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The Pentium 4 Processor and Intel Xeon Processor mask PMIs upon receiving an interrupt. Clear this condition 
before leaving the interrupt handler.

17.5 LAST 

BRANCH, 

INTERRUPT, 

AND EXCEPTION RECORDING (INTEL

®

 CORE™ 2 

DUO AND INTEL

®

 ATOM™ PROCESSORS)

The Intel Core 2 Duo processor family and Intel Xeon processors based on Intel Core microarchitecture or 
enhanced Intel Core microarchitecture provide last branch interrupt and exception recording. The facilities 
described in this section also apply to 45 nm and 32 nm Intel Atom processors. These capabilities are similar to 
those found in Pentium 4 processors, including support for the following facilities:

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Debug Trace and Branch Recording Control — The IA32_DEBUGCTL MSR provide bit fields for software to 
configure mechanisms related to debug trace, branch recording, branch trace store, and performance counter 
operations. See Section 17.4.1 for a description of the flags. See Figure 17-3 for the MSR layout.

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Last branch record (LBR) stack — There are a collection of MSR pairs that store the source and destination 
addresses related to recently executed branches. See Section 17.5.1. 

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Monitoring and single-stepping of branches, exceptions, and interrupts
— See Section 17.4.2 and Section 17.4.3. In addition, the ability to freeze the LBR stack on a PMI request is 

available.

— 45 nm and 32 nm Intel Atom processors clear the TR flag when the FREEZE_LBRS_ON_PMI flag is set.

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Branch trace messages — See Section 17.4.4. 

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Last exception records — See Section 17.11.3. 

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Branch trace store and CPL-qualified BTS — See Section 17.4.5.

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FREEZE_LBRS_ON_PMI flag (bit 11) — see Section 17.4.7 for legacy Freeze_LBRs_On_PMI operation. 

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FREEZE_PERFMON_ON_PMI flag (bit 12) — see Section 17.4.7 for legacy Freeze_Perfmon_On_PMI 
operation. 

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FREEZE_WHILE_SMM_EN (bit 14) — FREEZE_WHILE_SMM_EN is supported if 
IA32_PERF_CAPABILITIES.FREEZE_WHILE_SMM[Bit 12] is reporting 1. See Section 17.4.1.

17.5.1 LBR 

Stack 

The last branch record stack and top-of-stack (TOS) pointer MSRs are supported across Intel Core 2, Intel Atom 
processor families, and Intel processors based on Intel NetBurst microarchitecture. 
Four pairs of MSRs are supported in the LBR stack for Intel Core 2 processors families and Intel processors based 
on Intel NetBurst microarchitecture:

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Last Branch Record (LBR) Stack 
— MSR_LASTBRANCH_0_FROM_IP (address 40H) through MSR_LASTBRANCH_3_FROM_IP (address 43H) 

store source addresses

— MSR_LASTBRANCH_0_TO_IP (address 60H) through MSR_LASTBRANCH_3_TO_IP (address 63H) store 

destination addresses