4-44 Vol. 3A

PAGING

4.10.4.3   Optional Invalidation

The following items describe cases in which software may choose not to invalidate and the potential consequences 
of that choice:

•

If a paging-structure entry is modified to change the P flag from 0 to 1, no invalidation is necessary. This is 
because no TLB entry or paging-structure cache entry is created with information from a paging-structure entry 
in which the P flag is 0.

1

•

If a paging-structure entry is modified to change the accessed flag from 0 to 1, no invalidation is necessary 
(assuming that an invalidation was performed the last time the accessed flag was changed from 1 to 0). This is 
because no TLB entry or paging-structure cache entry is created with information from a paging-structure entry 
in which the accessed flag is 0.

•

If a paging-structure entry is modified to change the R/W flag from 0 to 1, failure to perform an invalidation 
may result in a “spurious” page-fault exception (e.g., in response to an attempted write access) but no other 
adverse behavior. Such an exception will occur at most once for each affected linear address (see Section 
4.10.4.1).

•

If CR4.SMEP = 0 and a paging-structure entry is modified to change the U/S flag from 0 to 1, failure to perform 
an invalidation may result in a “spurious” page-fault exception (e.g., in response to an attempted user-mode 
access) but no other adverse behavior. Such an exception will occur at most once for each affected linear 
address (see Section 4.10.4.1).

•

If a paging-structure entry is modified to change the XD flag from 1 to 0, failure to perform an invalidation may 
result in a “spurious” page-fault exception (e.g., in response to an attempted instruction fetch) but no other 
adverse behavior. Such an exception will occur at most once for each affected linear address (see Section 
4.10.4.1).

•

If a paging-structure entry is modified to change the accessed flag from 1 to 0, failure to perform an invali-
dation may result in the processor not setting that bit in response to a subsequent access to a linear address 
whose translation uses the entry. Software cannot interpret the bit being clear as an indication that such an 
access has not occurred.

•

If software modifies a paging-structure entry that identifies the final physical address for a linear address 
(either a PTE or a paging-structure entry in which the PS flag is 1) to change the dirty flag from 1 to 0, failure 
to perform an invalidation may result in the processor not setting that bit in response to a subsequent write to 
a linear address whose translation uses the entry. Software cannot interpret the bit being clear as an indication 
that such a write has not occurred.

•

The read of a paging-structure entry in translating an address being used to fetch an instruction may appear to 
execute before an earlier write to that paging-structure entry if there is no serializing instruction between the 
write and the instruction fetch. Note that the invalidating instructions identified in Section 4.10.4.1 are all 
serializing instructions.

•

Section 4.10.3.3 describes situations in which a single paging-structure entry may contain information cached 
in multiple entries in the paging-structure caches. Because all entries in these caches are invalidated by any 
execution of INVLPG, it is not necessary to follow the modification of such a paging-structure entry by 
executing INVLPG multiple times solely for the purpose of invalidating these multiple cached entries. (It may be 
necessary to do so to invalidate multiple TLB entries.)

4.10.4.4   Delayed Invalidation

Required invalidations may be delayed under some circumstances. Software developers should understand that, 
between the modification of a paging-structure entry and execution of the invalidation instruction recommended in 
Section 4.10.4.2, the processor may use translations based on either the old value or the new value of the paging-
structure entry. The following items describe some of the potential consequences of delayed invalidation:

•

If a paging-structure entry is modified to change the P flag from 1 to 0, an access to a linear address whose 
translation is controlled by this entry may or may not cause a page-fault exception.

1. If it is also the case that no invalidation was performed the last time the P flag was changed from 1 to 0, the processor may use a 

TLB entry or paging-structure cache entry that was created when the P flag had earlier been 1.