11-20 Vol. 3A

MEMORY CACHE CONTROL

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(Pentium 4, Intel Xeon, and later processors only.) Writing to control register CR4 to modify the PSE, PGE, or 
PAE flag.

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Writing to control register CR4 to change the PCIDE flag from 1 to 0.

See Section 4.10, “Caching Translation Information,” for additional information about the TLBs.

11.10 STORE 

BUFFER

Intel 64 and IA-32 processors temporarily store each write (store) to memory in a store buffer. The store buffer 
improves processor performance by allowing the processor to continue executing instructions without having to 
wait until a write to memory and/or to a cache is complete. It also allows writes to be delayed for more efficient use 
of memory-access bus cycles.
In general, the existence of the store buffer is transparent to software, even in systems that use multiple proces-
sors. The processor ensures that write operations are always carried out in program order. It also insures that the 
contents of the store buffer are always drained to memory in the following situations:

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When an exception or interrupt is generated.

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(P6 and more recent processor families only) When a serializing instruction is executed.

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When an I/O instruction is executed.

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When a LOCK operation is performed.

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(P6 and more recent processor families only) When a BINIT operation is performed.

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(Pentium III, and more recent processor families only) When using an SFENCE instruction to order stores.

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(Pentium 4 and more recent processor families only) When using an MFENCE instruction to order stores.

The discussion of write ordering in Section 8.2, “Memory Ordering,” gives a detailed description of the operation of 
the store buffer.

11.11  MEMORY TYPE RANGE REGISTERS (MTRRS)

The following section pertains only to the P6 and more recent processor families.
The memory type range registers (MTRRs) provide a mechanism for associating the memory types (see Section 
11.3, “Methods of Caching Available”) with physical-address ranges in system memory. They allow the processor 
to optimize operations for different types of memory such as RAM, ROM, frame-buffer memory, and memory-
mapped I/O devices. They also simplify system hardware design by eliminating the memory control pins used for 
this function on earlier IA-32 processors and the external logic needed to drive them.
The MTRR mechanism allows up to 96 memory ranges to be defined in physical memory, and it defines a set of 
model-specific registers (MSRs) for specifying the type of memory that is contained in each range. Table 11-8 
shows the memory types that can be specified and their properties; Figure 11-4 shows the mapping of physical 
memory with MTRRs. See Section 11.3, “Methods of Caching Available,” for a more detailed description of each 
memory type.
Following a hardware reset, the P6 and more recent processor families disable all the fixed and variable MTRRs, 
which in effect makes all of physical memory uncacheable. Initialization software should then set the MTRRs to a 
specific, system-defined memory map. Typically, the BIOS (basic input/output system) software configures the 
MTRRs. The operating system or executive is then free to modify the memory map using the normal page-level 
cacheability attributes.
In a multiprocessor system using a processor in the P6 family or a more recent family, each processor MUST use 
the identical MTRR memory map so that software will have a consistent view of memory.

NOTE

In multiple processor systems, the operating system must maintain MTRR consistency between all 
the processors in the system (that is, all processors must use the same MTRR values). The P6 and 
more recent processor families provide no hardware support for maintaining this consistency.