36-80 Vol. 3C

INTEL® PROCESSOR TRACE

(CTC

B

 - CTC

A

), where CTC

i

 = MTC

i

[15:8] << IA32_RTIT_CTL.MTCFreq and i = A, B. 

The time from a TSC packet to the subsequent MTC packet can be calculated using the TMA packet that follows the 
TSC packet. The TMA packet provides both the crystal clock value (lower 16 bits, in the CTC field) and the Adjust-
edProcessorCycles value (in the FastCounter field) that can be used in the calculation of the corresponding core 
crystal clock value of the TSC packet. 
When the next MTC after a pair of TSC/TMA is seen, the number of crystal clocks passed since the TSC packet can 
be calculated by subtracting the TMA.CTC value from the time indicated by the MTC

Next

 packet by 

CTC

Delta

[15:0] = (CTC

Next

[15:0] - TMA.CTC[15:0]), where CTC

Next

 = MTC

Payload

 << IA32_RTIT_CTL.MTCFreq.

The TMA.FastCounter field provides the fractional component of the TSC packet into the next crystal clock cycle. 
CYC packets can provide further precision of an estimated timestamp value to many non-timing packets, by 
providing an indication of the time passed between other timing packets (MTCs or TSCs). 
When enabled, CYC packets are sent preceding each CYC-eligible packet, and provide the number of processor core 
clock cycles that have passed since the last CYC packet. Thus between MTCs and TSCs, the accumulated CYC 
values can be used to estimate the adjusted_processor_cycles component of the timestamp value. The accumu-
lated CPU cycles will have to be adjusted to account for the difference in frequency between the processor core 
clock and the P1 frequency. The necessary adjustment can be estimated using the core:bus ratio value given in the 
CBR packet, by multiplying the accumulated cycle count value by P1/CBR

payload

. 

A greater level of precision may be achieved by calculating the CPU clock frequency, see Section 36.8.3.4 below for 
a method to do so using Intel PT packets. 
CYCs can be used to estimate time between TSCs even without MTCs, though this will likely result in a reduction in 
estimated TSC precision.

36.8.3.3   VMX TSC Manipulation

When software executes in non-Root operation, additional offset and scaling factors may be applied to the TSC 
value. These are optional, but may be enabled via VMCS controls on a per-VM basis. See Chapter 25, “VMX Non-
Root Operation” for details on VMX TSC offsetting and TSC scaling.
Like the value returned by RDTSC, TSC packets will include these adjustments, but other timing packets (such as 
MTC, CYC, and CBR) are not impacted. In order to use the algorithm above to estimate the TSC value when TSC 
scaling is in use, it will be necessary for software to account for the scaling factor. See Section 36.5.2.6 for details.

36.8.3.4   Calculating Frequency with Intel PT

Because Intel PT can provide both wall-clock time and processor clock cycle time, it can be used to measure the 
processor core clock frequency. Either TSC or MTC packets can be used to track the wall-clock time. By using CYC 
packets to count the number of processor core cycles that pass in between a pair of wall-clock time packets, the 
ratio between processor core clock frequency and TSC frequency can be derived. If the P1 frequency is known, it 
can be applied to determine the CPU frequency. See Section 36.8.3.1 above for details on the relationship between 
TSC, MTC, and CYC.