Vol. 3D A-1

APPENDIX A

VMX CAPABILITY REPORTING FACILITY

The ability of a processor to support VMX operation and related instructions is indicated by 
CPUID.1:ECX.VMX[bit 5] = 1. A value 1 in this bit indicates support for VMX features.
Support for specific features detailed in Chapter 26 and other VMX chapters is determined by reading values from 
a set of capability MSRs. These MSRs are indexed starting at MSR address 480H. VMX capability MSRs are read-
only; an attempt to write them (with WRMSR) produces a general-protection exception (#GP(0)). They do not exist 
on processors that do not support VMX operation; an attempt to read them (with RDMSR) on such processors 
produces a general-protection exception (#GP(0)).

A.1 

BASIC VMX INFORMATION

The IA32_VMX_BASIC MSR (index 480H) consists of the following fields:

•

Bits 30:0 contain the 31-bit VMCS revision identifier used by the processor. Processors that use the same VMCS 
revision identifier use the same size for VMCS regions (see subsequent item on bits 44:32).

1

•

Bit 31 is always 0.

•

Bits 44:32 report the number of bytes that software should allocate for the VMXON region and any VMCS 
region. It is a value greater than 0 and at most 4096 (bit 44 is set if and only if bits 43:32 are clear).

•

Bit 48 indicates the width of the physical addresses that may be used for the VMXON region, each VMCS, and 
data structures referenced by pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX transi-
tions). If the bit is 0, these addresses are limited to the processor’s physical-address width.

2

 If the bit is 1, 

these addresses are limited to 32 bits. This bit is always 0 for processors that support Intel 64 architecture.

•

If bit 49 is read as 1, the logical processor supports the dual-monitor treatment of system-management 
interrupts and system-management mode. See Section 34.15 for details of this treatment.

•

Bits 53:50 report the memory type that should be used for the VMCS, for data structures referenced by 
pointers in the VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX transitions), and for the MSEG 
header. If software needs to access these data structures (e.g., to modify the contents of the MSR bitmaps), it 
can configure the paging structures to map them into the linear-address space. If it does so, it should establish 
mappings that use the memory type reported bits 53:50 in this MSR.

3

As of this writing, all processors that support VMX operation indicate the write-back type. The values used are 
given in Table A-1.

1. Earlier versions of this manual specified that the VMCS revision identifier was a 32-bit field in bits 31:0 of this MSR. For all proces-

sors produced prior to this change, bit 31 of this MSR was read as 0.

2. On processors that support Intel 64 architecture, the pointer must not set bits beyond the processor's physical address width.
3. Alternatively, software may map any of these regions or structures with the UC memory type. (This may be necessary for the MSEG 

header.) Doing so is discouraged unless necessary as it will cause the performance of software accesses to those structures to suf-

fer.

Table A-1.  Memory Types Recommended for VMCS and Related Data Structures

Value(s)

Field

0

Uncacheable (UC)

1–5

Not used

6

Write Back (WB)

7–15

Not used