18-20 Vol. 3B

PERFORMANCE MONITORING

18.4.3 At-Retirement 

Events

Many non-architectural performance events are impacted by the speculative nature of out-of-order execution. A 
subset of non-architectural performance events on processors based on Intel Core microarchitecture are enhanced 
with a tagging mechanism (similar to that found in Intel NetBurst

®

 microarchitecture) that exclude contributions 

that arise from speculative execution. The at-retirement events available in processors based on Intel Core micro-
architecture does not require special MSR programming control (see Section 18.15.6, “At-Retirement Counting”), 
but is limited to IA32_PMC0. See Table 18-9 for a list of events available to processors based on Intel Core micro-
architecture.

18.4.4 

Processor Event Based Sampling (PEBS)

Processors based on Intel Core microarchitecture also support processor event based sampling (PEBS). This 
feature was introduced by processors based on Intel NetBurst microarchitecture.
PEBS uses a debug store mechanism and a performance monitoring interrupt to store a set of architectural state 
information for the processor. The information provides architectural state of the instruction executed after the 
instruction that caused the event (See Section 18.4.4.2 and Section 17.4.9). 
In cases where the same instruction causes BTS and PEBS to be activated, PEBS is processed before BTS are 
processed. The PMI request is held until the processor completes processing of PEBS and BTS.
For processors based on Intel Core microarchitecture, precise events that can be used with PEBS are listed in 
Table 18-10. The procedure for detecting availability of PEBS is the same as described in Section 18.15.7.1.

Table 18-9.  At-Retirement Performance Events for Intel Core Microarchitecture

Event Name

UMask

Event Select

ITLB_MISS_RETIRED

00H

C9H

MEM_LOAD_RETIRED.L1D_MISS

01H

CBH

MEM_LOAD_RETIRED.L1D_LINE_MISS

02H

CBH

MEM_LOAD_RETIRED.L2_MISS

04H

CBH

MEM_LOAD_RETIRED.L2_LINE_MISS

08H

CBH

MEM_LOAD_RETIRED.DTLB_MISS

10H

CBH

Table 18-10.  PEBS Performance Events for Intel Core Microarchitecture

Event Name

UMask

Event Select

INSTR_RETIRED.ANY_P

00H

C0H

X87_OPS_RETIRED.ANY

FEH

C1H

BR_INST_RETIRED.MISPRED

00H

C5H

SIMD_INST_RETIRED.ANY

1FH

C7H

MEM_LOAD_RETIRED.L1D_MISS

01H

CBH

MEM_LOAD_RETIRED.L1D_LINE_MISS

02H

CBH

MEM_LOAD_RETIRED.L2_MISS

04H

CBH

MEM_LOAD_RETIRED.L2_LINE_MISS

08H

CBH

MEM_LOAD_RETIRED.DTLB_MISS

10H

CBH