Vol. 3D A-7
VMX CAPABILITY REPORTING FACILITY
0 (with value 0 in both MSRs), fixed to 1 (1 in both MSRs), or flexible (0 in IA32_VMX_CR4_FIXED0 and 1 in
IA32_VMX_CR4_FIXED1).
A.9 VMCS
ENUMERATION
The IA32_VMX_VMCS_ENUM MSR (index 48AH) provides information to assist software in enumerating fields in
the VMCS.
As noted in Section 24.11.2, each field in the VMCS is associated with a 32-bit encoding which is structured as
follows:
•
Bits 31:15 are reserved (must be 0).
•
Bits 14:13 indicate the field’s width.
•
Bit 12 is reserved (must be 0).
•
Bits 11:10 indicate the field’s type.
•
Bits 9:1 is an index field that distinguishes different fields with the same width and type.
•
Bit 0 indicates access type.
IA32_VMX_VMCS_ENUM indicates to software the highest index value used in the encoding of any field supported
by the processor:
•
Bits 9:1 contain the highest index value used for any VMCS encoding.
•
Bit 0 and bits 63:10 are reserved and are read as 0.
A.10
VPID AND EPT CAPABILITIES
The IA32_VMX_EPT_VPID_CAP MSR (index 48CH) reports information about the capabilities of the logical
processor with regard to virtual-processor identifiers (VPIDs, Section 28.1) and extended page tables (EPT, Section
28.2):
•
If bit 0 is read as 1, the logical processor allows software to configure EPT paging-structure entries in which
bits 2:0 have value 100b (indicating an execute-only translation).
•
Bit 6 indicates support for a page-walk length of 4.
•
If bit 8 is read as 1, the logical processor allows software to configure the EPT paging-structure memory type
to be uncacheable (UC); see Section 24.6.11.
•
If bit 14 is read as 1, the logical processor allows software to configure the EPT paging-structure memory type
to be write-back (WB).
•
If bit 16 is read as 1, the logical processor allows software to configure a EPT PDE to map a 2-Mbyte page (by
setting bit 7 in the EPT PDE).
•
If bit 17 is read as 1, the logical processor allows software to configure a EPT PDPTE to map a 1-Gbyte page (by
setting bit 7 in the EPT PDPTE).
•
Support for the INVEPT instruction (see Chapter 30 and Section 28.3.3.1).
— If bit 20 is read as 1, the INVEPT instruction is supported.
— If bit 25 is read as 1, the single-context INVEPT type is supported.
— If bit 26 is read as 1, the all-context INVEPT type is supported.
•
If bit 21 is read as 1, accessed and dirty flags for EPT are supported (see Section 28.2.4).
•
Support for the INVVPID instruction (see Chapter 30 and Section 28.3.3.1).
— If bit 32 is read as 1, the INVVPID instruction is supported.
— If bit 40 is read as 1, the individual-address INVVPID type is supported.
— If bit 41 is read as 1, the single-context INVVPID type is supported.