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Vol. 3A 4-43

PAGING   Recommended Invalidation

The following items provide some recommendations regarding when software should perform invalidations:

If software modifies a paging-structure entry that maps a page (rather than referencing another paging 
structure), it should execute INVLPG for any linear address with a page number whose translation uses that 
paging-structure entry.


(If the paging-structure entry may be used in the translation of different page numbers — see Section 
— software should execute INVLPG for linear addresses with each of those page numbers; alternatively, it could 
use MOV to CR3 or MOV to CR4.)

If software modifies a paging-structure entry that references another paging structure, it may use one of the 
following approaches depending upon the types and number of translations controlled by the modified entry:
— Execute INVLPG for linear addresses with each of the page numbers with translations that would use the 

entry. However, if no page numbers that would use the entry have translations (e.g., because the P flags 
are 0 in all entries in the paging structure referenced by the modified entry), it remains necessary to 
execute INVLPG at least once.

— Execute MOV to CR3 if the modified entry controls no global pages.
— Execute MOV to CR4 to modify CR4.PGE.

If CR4.PCIDE = 1 and software modifies a paging-structure entry that does not map a page or in which the G 
flag (bit 8) is 0, additional steps are required if the entry may be used for PCIDs other than the current one. Any 
one of the following suffices:
— Execute MOV to CR4 to modify CR4.PGE, either immediately or before again using any of the affected 

PCIDs. For example, software could use different (previously unused) PCIDs for the processes that used the 
affected PCIDs.

— For each affected PCID, execute MOV to CR3 to make that PCID current (and to load the address of the 

appropriate PML4 table). If the modified entry controls no global pages and bit 63 of the source operand to 
MOV to CR3 was 0, no further steps are required. Otherwise, execute INVLPG for linear addresses with each 
of the page numbers with translations that would use the entry; if no page numbers that would use the 
entry have translations, execute INVLPG at least once.

If software using PAE paging modifies a PDPTE, it should reload CR3 with the register’s current value to ensure 
that the modified PDPTE is loaded into the corresponding PDPTE register (see Section 4.4.1).

If the nature of the paging structures is such that a single entry may be used for multiple purposes (see Section,
 software should perform invalidations for all of these purposes. For example, if a single entry might 
serve as both a PDE and PTE, it may be necessary to execute INVLPG with two (or more) linear addresses, one 
that uses the entry as a PDE and one that uses it as a PTE. (Alternatively, software could use MOV to CR3 or 
MOV to CR4.)

As noted in Section 4.10.2, the TLBs may subsequently contain multiple translations for the address range if 
software modifies the paging structures so that the page size used for a 4-KByte range of linear addresses 
changes. A reference to a linear address in the address range may use any of these translations.
Software wishing to prevent this uncertainty should not write to a paging-structure entry in a way that would 
change, for any linear address, both the page size and either the page frame, access rights, or other attributes. 
It can instead use the following algorithm: first clear the P flag in the relevant paging-structure entry (e.g., 
PDE); then invalidate any translations for the affected linear addresses (see above); and then modify the 
relevant paging-structure entry to set the P flag and establish modified translation(s) for the new page size.

Software should clear bit 63 of the source operand to a MOV to CR3 instruction that establishes a PCID that had 
been used earlier for a different linear-address space (e.g., with a different value in bits 51:12 of CR3). This 
ensures invalidation of any information that may have been cached for the previous linear-address space.
This assumes that both linear-address spaces use the same global pages and that it is thus not necessary to 
invalidate any global TLB entries. If that is not the case, software should invalidate those entries by executing 
MOV to CR4 to modify CR4.PGE.

1. One execution of INVLPG is sufficient even for a page with size greater than 4 KBytes.