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Vol. 3A 4-35


For an access to the physical address that is the translation of a linear address, = 4*PAT+2*PCD+PWT, where 
the PAT, PCD, and PWT values come from the relevant PTE (if the translation uses a 4-KByte page), the relevant 
PDE (if the translation uses a 2-MByte page or a 4-MByte page), or the relevant PDPTE (if the translation uses 
a 1-GByte page).

With PAE paging, the WB memory type is used when loading the PDPTEs (see Section 4.4.1).



Caching Paging-Related Information about Memory Typing

A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see 

Section 4.10). These structures may include information about memory typing. The processor may use memory-

typing information from the TLBs and paging-structure caches instead of from the paging structures in memory.
This fact implies that, if software modifies a paging-structure entry to change the memory-typing bits, the 
processor might not use that change for a subsequent translation using that entry or for access to an affected 
linear address. See Section for how software can ensure that the processor uses the modified memory 



The Intel-64 and IA-32 architectures may accelerate the address-translation process by caching data from the 
paging structures on the processor. Because the processor does not ensure that the data that it caches are always 
consistent with the structures in memory, it is important for software developers to understand how and when the 
processor may cache such data. They should also understand what actions software can take to remove cached 
data that may be inconsistent and when it should do so. This section provides software developers information 
about the relevant processor operation.
Section 4.10.1 introduces process-context identifiers (PCIDs), which a logical processor may use to distinguish 
information cached for different linear-address spaces. Section 4.10.2 and Section 4.10.3 describe how the 
processor may cache information in translation lookaside buffers (TLBs) and paging-structure caches, respectively. 
Section 4.10.4 explains how software can remove inconsistent cached information by invalidating portions of the 
TLBs and paging-structure caches. Section 4.10.5 describes special considerations for multiprocessor systems.


Process-Context Identifiers (PCIDs)

Process-context identifiers (PCIDs) are a facility by which a logical processor may cache information for multiple 
linear-address spaces. The processor may retain cached information when software switches to a different linear-
address space with a different PCID (e.g., by loading CR3; see Section for details).
A PCID is a 12-bit identifier. Non-zero PCIDs are enabled by setting the PCIDE flag (bit 17) of CR4. If CR4.PCIDE = 
0, the current PCID is always 000H; otherwise, the current PCID is the value of bits 11:0 of CR3. Not all processors 
allow CR4.PCIDE to be set to 1; see Section 4.1.4 for how to determine whether this is allowed.
The processor ensures that CR4.PCIDE can be 1 only in IA-32e mode (thus, 32-bit paging and PAE paging use only 
PCID 000H). In addition, software can change CR4.PCIDE from 0 to 1 only if CR3[11:0] = 000H. These require-
ments are enforced by the following limitations on the MOV CR instruction:

MOV to CR4 causes a general-protection exception (#GP) if it would change CR4.PCIDE from 0 to 1 and either 
IA32_EFER.LMA = 0 or CR3[11:0] ≠ 000H.

MOV to CR0 causes a general-protection exception if it would clear CR0.PG to 0 while CR4.PCIDE = 1.

When a logical processor creates entries in the TLBs (Section 4.10.2) and paging-structure caches (Section 
4.10.3), it 
associates those entries with the current PCID. When using entries in the TLBs and paging-structure 
caches to translate a linear address, a logical processor uses only those entries associated with the current PCID 
(see Section for an exception).

1. Some older IA-32 processors used the UC memory type when loading the PDPTEs. Some processors may use the UC memory type if 

CR0.CD = 1 or if the MTRRs are disabled. These behaviors are model-specific and not architectural.