8-28 Vol. 3A

MULTIPLE-PROCESSOR MANAGEMENT

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Memory type range registers (MTRRs)

Whether the following features are shared or duplicated is implementation-specific:

•

IA32_MISC_ENABLE MSR (MSR address 1A0H)

•

Machine check architecture (MCA) MSRs (except for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs)

•

Performance monitoring control and counter MSRs

8.7.2 APIC 

Functionality

When a processor supporting Intel Hyper-Threading Technology support is initialized, each logical processor is 
assigned a local APIC ID (see Table 10-1). The local APIC ID serves as an ID for the logical processor and is stored 
in the logical processor’s APIC ID register. If two or more processors supporting Intel Hyper-Threading Technology 
are present in a dual processor (DP) or MP system, each logical processor on the system bus is assigned a unique 
local APIC ID (see Section 8.9.3, “Hierarchical ID of Logical Processors in an MP System”).
Software communicates with local processors using the APIC’s interprocessor interrupt (IPI) messaging facility. 
Setup and programming for APICs is identical in processors that support and do not support Intel Hyper-Threading 
Technology. See Chapter 10, “Advanced Programmable Interrupt Controller (APIC),” for a detailed discussion.

8.7.3 

Memory Type Range Registers (MTRR)

MTRRs in a processor supporting Intel Hyper-Threading Technology are shared by logical processors. When one 
logical processor updates the setting of the MTRRs, settings are automatically shared with the other logical proces-
sors in the same physical package. 
The architectures require that all MP systems based on Intel 64 and IA-32 processors (this includes logical proces-
sors) must use an identical MTRR memory map. This gives software a consistent view of memory, independent of 
the processor on which it is running. See Section 11.11, “Memory Type Range Registers (MTRRs),” for information 
on setting up MTRRs.

8.7.4 

Page Attribute Table (PAT)

Each logical processor has its own PAT MSR (IA32_PAT). However, as described in Section 11.12, “Page Attribute 
Table (PAT),” the PAT MSR settings must be the same for all processors in a system, including the logical proces-
sors.

8.7.5 

Machine Check Architecture

In the Intel HT Technology context as implemented by processors based on Intel NetBurst

®

 microarchitecture, all 

of the machine check architecture (MCA) MSRs (except for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs) are 
duplicated for each logical processor. This permits logical processors to initialize, configure, query, and handle 
machine-check exceptions simultaneously within the same physical processor. The design is compatible with 
machine check exception handlers that follow the guidelines given in Chapter 15, “Machine-Check Architecture.”
The IA32_MCG_STATUS MSR is duplicated for each logical processor so that its machine check in progress bit field 
(MCIP) can be used to detect recursion on the part of MCA handlers. In addition, the MSR allows each logical 
processor to determine that a machine-check exception is in progress independent of the actions of another logical 
processor in the same physical package.
Because the logical processors within a physical package are tightly coupled with respect to shared hardware 
resources, both logical processors are notified of machine check errors that occur within a given physical processor. 
If machine-check exceptions are enabled when a fatal error is reported, all the logical processors within a physical 
package are dispatched to the machine-check exception handler. If machine-check exceptions are disabled, the 
logical processors enter the shutdown state and assert the IERR# signal.
When enabling machine-check exceptions, the MCE flag in control register CR4 should be set for each logical 
processor.