26-22 Vol. 3C

VM ENTRIES

— If the VM entry was executed in SMM, SMIs are blocked after VM entry if and only if the bit 2 in the inter-

ruptibility-state field is 1.

26.6.2 Activity 

State

The activity-state field in the guest-state area controls whether, after VM entry, the logical processor is active or in 
one of the inactive states identified in Section 24.4.2. The use of this field is determined as follows:

•

If the VM entry is vectoring, the logical processor is in the active state after VM entry. While the consistency 
checks described in Section 26.3.1.5 on the activity-state field do apply in this case, the contents of the 
activity-state field do not determine the activity state after VM entry.

•

If the VM entry is not vectoring, the logical processor ends VM entry in the activity state specified in the guest-
state area. If VM entry ends with the logical processor in an inactive activity state, the VM entry generates any 
special bus cycle that is normally generated when that activity state is entered from the active state. If 
VM entry would end with the logical processor in the shutdown state and the logical processor is in SMX 
operation,

1

 an Intel

®

 TXT shutdown condition occurs. The error code used is 0000H, indicating “legacy 

shutdown.” See Intel

®

 Trusted Execution Technology Preliminary Architecture Specification.

•

Some activity states unconditionally block certain events. The following blocking is in effect after any VM entry 
that puts the processor in the indicated state:
— The active state blocks start-up IPIs (SIPIs). SIPIs that arrive while a logical processor is in the active state 

and in VMX non-root operation are discarded and do not cause VM exits.

— The HLT state blocks start-up IPIs (SIPIs). SIPIs that arrive while a logical processor is in the HLT state and 

in VMX non-root operation are discarded and do not cause VM exits.

— The shutdown state blocks external interrupts and SIPIs. External interrupts that arrive while a logical 

processor is in the shutdown state and in VMX non-root operation do not cause VM exits even if the 
“external-interrupt exiting” VM-execution control is 1. SIPIs that arrive while a logical processor is in the 
shutdown state and in VMX non-root operation are discarded and do not cause VM exits.

— The wait-for-SIPI state blocks external interrupts, non-maskable interrupts (NMIs), INIT signals, and 

system-management interrupts (SMIs). Such events do not cause VM exits if they arrive while a logical 
processor is in the wait-for-SIPI state and in VMX non-root operation do not cause VM exits regardless of 
the settings of the pin-based VM-execution controls.

26.6.3 

Delivery of Pending Debug Exceptions after VM Entry

The pending debug exceptions field in the guest-state area indicates whether there are debug exceptions that have 
not yet been delivered (see Section 24.4.2). This section describes how these are treated on VM entry.
There are no pending debug exceptions after VM entry if any of the following are true:

•

The VM entry is vectoring with one of the following interruption types: external interrupt, non-maskable 
interrupt (NMI), hardware exception, or privileged software exception.

•

The interruptibility-state field does not indicate blocking by MOV SS and the VM entry is vectoring with either 
of the following interruption type: software interrupt or software exception.

•

The VM entry is not vectoring and the activity-state field indicates either shutdown or wait-for-SIPI.

If none of the above hold, the pending debug exceptions field specifies the debug exceptions that are pending for 
the guest. There are valid pending debug exceptions if either the BS bit (bit 14) or the enable-breakpoint bit 
(bit 12) is 1. If there are valid pending debug exceptions, they are handled as follows:

•

If the VM entry is not vectoring, the pending debug exceptions are treated as they would had they been 
encountered normally in guest execution:
— If the logical processor is not blocking such exceptions (the interruptibility-state field indicates no blocking 

by MOV SS), a debug exception is delivered after VM entry (see below). 

1. A logical processor is in SMX operation if GETSEC[SEXIT] has not been executed since the last execution of GETSEC[SENTER]. See 

Chapter 6, “Safer Mode Extensions Reference,” in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.