10-14 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Interrupt Input Pin Polarity
Specifies the polarity of the corresponding interrupt pin: (0) active high or (1) active low.
Remote IRR Flag (Read Only)
For fixed mode, level-triggered interrupts; this flag is set when the local APIC accepts the
interrupt for servicing and is reset when an EOI command is received from the processor. The
meaning of this flag is undefined for edge-triggered interrupts and other delivery modes.
Trigger Mode
Selects the trigger mode for the local LINT0 and LINT1 pins: (0) edge sensitive and (1) level
sensitive. This flag is only used when the delivery mode is Fixed. When the delivery mode is
NMI, SMI, or INIT, the trigger mode is always edge sensitive. When the delivery mode is
ExtINT, the trigger mode is always level sensitive. The timer and error interrupts are always
treated as edge sensitive.
If the local APIC is not used in conjunction with an I/O APIC and fixed delivery mode is
selected; the Pentium 4, Intel Xeon, and P6 family processors will always use level-sensitive
triggering, regardless if edge-sensitive triggering is selected.
Software should always set the trigger mode in the LVT LINT1 register to 0 (edge sensitive).
Level-sensitive interrupts are not supported for LINT1.
Mask
Interrupt mask: (0) enables reception of the interrupt and (1) inhibits reception of the inter-
rupt. When the local APIC handles a performance-monitoring counters interrupt, it automati-
cally sets the mask flag in the LVT performance counter register. This flag is set to 1 on reset.
It can be cleared only by software.
Timer Mode
Bits 18:17 selects the timer mode (see Section 10.5.4):
(00b) one-shot mode using a count-down value,
(01b) periodic mode reloading a count-down value,
(10b) TSC-Deadline mode using absolute target value in IA32_TSC_DEADLINE MSR (see
(11b) is reserved.
10.5.2
Valid Interrupt Vectors
The Intel 64 and IA-32 architectures define 256 vector numbers, ranging from 0 through 255 (see Section 6.2,
“Exception and Interrupt Vectors”). Local and I/O APICs support 240 of these vectors (in the range of 16 to 255) as
valid interrupts.
When an interrupt vector in the range of 0 to 15 is sent or received through the local APIC, the APIC indicates an
illegal vector in its Error Status Register (see Section 10.5.3, “Error Handling”). The Intel 64 and IA-32 architec-
tures reserve vectors 16 through 31 for predefined interrupts, exceptions, and Intel-reserved encodings (see Table
6-1). However, the local APIC does not treat vectors in this range as illegal.
When an illegal vector value (0
to 15) is written to an LVT entry and the delivery mode is Fixed (bits 8-11
equal 0),
the APIC may signal an illegal vector error, without regard to whether the mask bit is set or whether an interrupt is
actually seen on the input.
10.5.3 Error
Handling
The local APIC records errors detected during interrupt handling in the error status register (ESR). The format of
the ESR is given in Figure 10-9; it contains the following flags:
•
Bit 0: Send Checksum Error.
Set when the local APIC detects a checksum error for a message that it sent on the APIC bus. Used only on P6
family and Pentium processors.
•
Bit 1: Receive Checksum Error.
Set when the local APIC detects a checksum error for a message that it received on the APIC bus. Used only on
P6 family and Pentium processors.