18-12 Vol. 3B

PERFORMANCE MONITORING

Effectively, the IA32_PERF_GLOBAL_STATUS.CTR_FRZ bit also serve as an read-only control to enable 
programmable performance counters and fixed counters in the core PMU. To enable counting with the 
performance counters, the following expression must hold with architectural perfmon version 4 or higher:

•

(IA32_PERFEVTSELn.EN & IA32_PERF_GLOBAL_CTRL.PMCn & 

(!IA32_PERF_GLOBAL_STATUS.CTR_FRZ) ) = 1 for programmable counter ‘n’, or 

•

(IA32_PERF_FIXED_CRTL.ENi & IA32_PERF_GLOBAL_CTRL.FCi & 

(!IA32_PERF_GLOBAL_STATUS.CTR_FRZ) ) = 1 for fixed counter ‘i’

The read-only enable interface IA32_PERF_GLOBAL_STATUS.CTR_FRZ provides a more efficient flow for a PMI 
handler to use IA32_DEBUGCTL.Freeza_Perfmon_On_PMI to filter out data that may distort target workload anal-
ysis, see Table 17-3. It should be noted the IA32_PERF_GLOBAL_CTRL register continue to serve as the primary 
interface to control all performance counters of the logical processor. 
For example, when the Freeze-On-PMI mode is not being used, a PMI handler would be setting 
IA32_PERF_GLOBAL_CTRL as the very last step to commence the overall operation after configuring the individual 
counter registers, controls and PEBS facility. This does not only assure atomic monitoring but also avoids unneces-
sary complications (e.g. race conditions) when software attempts to change the core PMU configuration while some 
counters are kept enabled.
Additionally, IA32_PERF_GLOBAL_STATUS.TraceToPAPMI[bit 55]: On processors that support Intel Processor Trace 
and configured to store trace output packets to physical memory using the ToPA scheme, bit 55 is set when a PMI 
occurred due to a ToPA entry memory buffer was completely filled. 
IA32_PERF_GLOBAL_STATUS also provides an indicator to distinguish interaction of performance monitoring oper-
ations with other side-band activities, which apply Intel SGX on processors that support SGX (For additional infor-
mation about Intel SGX, see “Intel® Software Guard Extensions Programming Reference”.):

•

IA32_PERF_GLOBAL_STATUS.ASCI[bit 60]: This bit is set when data accumulated in any of the configured 
performance counters (i.e. IA32_PMCx or IA32_

FIXED_CTRx) may include contributions from direct or indirect 

operation of Intel SGX to protect an enclave (since the last time IA32_PERF_GLOBAL_STATUS.ASCI was 
cleared). 

Note, a processor’s support for IA32_PERF_GLOBAL_STATUS.TraceToPAPMI[bit 55] is enumerated as a result of 
CPUID enumerated capability of Intel Processor Trace and the use of the ToPA buffer scheme. Support of 
IA32_PERF_GLOBAL_STATUS.ASCI[bit 60] is enumerated by the CPUID enumeration of Intel SGX.

18.2.4.2   IA32_PERF_GLOBAL_STATUS_RESET and IA32_PERF_GLOBAL_STATUS_SET MSRS

With architectural performance monitoring version 3 and lower, clearing of the set bits in 
IA32_PERF_GLOBAL_STATUS MSR by software is done via IA32_PERF_GLOBAL_OVF_CTRL MSR. Starting with 
architectural performance monitoring version 4, software can manage the overflow and other indicators in 
IA32_PERF_GLOBAL_STATUS using separate interfaces to set or clear individual bits. 

Figure 18-10.  IA32_PERF_GLOBAL_STATUS MSR and Architectural Perfmon Version 4

Reserved

62

IA32_FIXED_CTR2 Overflow
IA32_FIXED_CTR1 Overflow
IA32_FIXED_CTR0 Overflow

TraceToPAPMI

.. 1 0

IA32_PMC0 Overflow

31

32

33

34

35

63

CondChgd
OvfDSBuffer

..

N

...................... Overflow

IA32_PMC(N-1) Overflow

OvfUncore

61

IA32_PMC1 Overflow

60 59 58

55

ASCI

LBR_Frz

CTR_Frz