Vol. 3B 17-1

CHAPTER 17

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING

FEATURES

Intel 64 and IA-32 architectures provide debug facilities for use in debugging code and monitoring performance. 
These facilities are valuable for debugging application software, system software, and multitasking operating 
systems. Debug support is accessed using debug registers (DR0 through DR7) and model-specific registers 
(MSRs): 

•

Debug registers hold the addresses of memory and I/O locations called breakpoints. Breakpoints are user-
selected locations in a program, a data-storage area in memory, or specific I/O ports. They are set where a 
programmer or system designer wishes to halt execution of a program and examine the state of the processor 
by invoking debugger software. A debug exception (#DB) is generated when a memory or I/O access is made 
to a breakpoint address. 

•

MSRs monitor branches, interrupts, and exceptions; they record addresses of the last branch, interrupt or 
exception taken and the last branch taken before an interrupt or exception.

•

Time stamp counter is described in Section 17.15, “Time-Stamp Counter”.

•

Features which allow monitoring of shared platform resources such as the L3 cache are described in Section 
17.16, “Intel® Resource Director Technology (Intel® RDT) Monitoring Features”.

•

Features which enable control over shared platform resources are described in Section 17.17, “Intel® Resource 
Director Technology (Intel® RDT) Allocation Features”.

17.1 

OVERVIEW OF DEBUG SUPPORT FACILITIES

The following processor facilities support debugging and performance monitoring:

•

Debug exception (#DB) — Transfers program control to a debug procedure or task when a debug event 
occurs.

•

Breakpoint exception (#BP) — See breakpoint instruction (INT 3) below.

•

Breakpoint-address registers (DR0 through DR3) — Specifies the addresses of up to 4 breakpoints.

•

Debug status register (DR6) — Reports the conditions that were in effect when a debug or breakpoint 
exception was generated.

•

Debug control register (DR7) — Specifies the forms of memory or I/O access that cause breakpoints to be 
generated.

•

T (trap) flag, TSS — Generates a debug exception (#DB) when an attempt is made to switch to a task with 
the T flag set in its TSS.

•

RF (resume) flag, EFLAGS register — Suppresses multiple exceptions to the same instruction.

•

TF (trap) flag, EFLAGS register — Generates a debug exception (#DB) after every execution of an 
instruction.

•

Breakpoint instruction (INT 3) — Generates a breakpoint exception (#BP) that transfers program control to 
the debugger procedure or task. This instruction is an alternative way to set code breakpoints. It is especially 
useful when more than four breakpoints are desired, or when breakpoints are being placed in the source code.

•

Last branch recording facilities — Store branch records in the last branch record (LBR) stack MSRs for the 
most recent taken branches, interrupts, and/or exceptions in MSRs. A branch record consist of a branch-from 
and a branch-to instruction address. Send branch records out on the system bus as branch trace messages 
(BTMs).

These facilities allow a debugger to be called as a separate task or as a procedure in the context of the current 
program or task. The following conditions can be used to invoke the debugger:

•

Task switch to a specific task.

•

Execution of the breakpoint instruction.