18-118 Vol. 3B

PERFORMANCE MONITORING

18.22.4  Event and Time-Stamp Monitoring Software

To use the performance-monitoring counters and time-stamp counter, the operating system needs to provide an 
event-monitoring device driver. This driver should include procedures for handling the following operations:

•

Feature checking

•

Initialize and start counters

•

Stop counters

•

Read the event counters

•

Read the time-stamp counter

The event monitor feature determination procedure must check whether the current processor supports the perfor-
mance-monitoring counters and time-stamp counter. This procedure compares the family and model of the 
processor returned by the CPUID instruction with those of processors known to support performance monitoring. 
(The Pentium and P6 family processors support performance counters.) The procedure also checks the MSR and 
TSC flags returned to register EDX by the CPUID instruction to determine if the MSRs and the RDTSC instruction are 
supported.
The initialize and start counters procedure sets the PerfEvtSel0 and/or PerfEvtSel1 MSRs for the events to be 
counted and the method used to count them and initializes the counter MSRs (PerfCtr0 and PerfCtr1) to starting 
counts. The stop counters procedure stops the performance counters (see Section 18.22.3, “Starting and Stopping 
the Performance-Monitoring Counters”).
The read counters procedure reads the values in the PerfCtr0 and PerfCtr1 MSRs, and a read time-stamp counter 
procedure reads the time-stamp counter. These procedures would be provided in lieu of enabling the RDTSC and 
RDPMC instructions that allow application code to read the counters. 

18.22.5  Monitoring Counter Overflow

The P6 family processors provide the option of generating a local APIC interrupt when a performance-monitoring 
counter overflows. This mechanism is enabled by setting the interrupt enable flag in either the PerfEvtSel0 or the 
PerfEvtSel1 MSR. The primary use of this option is for statistical performance sampling. 
To use this option, the operating system should do the following things on the processor for which performance 
events are required to be monitored:

•

Provide an interrupt vector for handling the counter-overflow interrupt.

•

Initialize the APIC PERF local vector entry to enable handling of performance-monitor counter overflow events.

•

Provide an entry in the IDT that points to a stub exception handler that returns without executing any instruc-
tions.

•

Provide an event monitor driver that provides the actual interrupt handler and modifies the reserved IDT entry 
to point to its interrupt routine.

When interrupted by a counter overflow, the interrupt handler needs to perform the following actions:

•

Save the instruction pointer (EIP register), code-segment selector, TSS segment selector, counter values and 
other relevant information at the time of the interrupt.

•

Reset the counter to its initial setting and return from the interrupt.

An event monitor application utility or another application program can read the information collected for analysis 
of the performance of the profiled application.

18.23  PERFORMANCE MONITORING (PENTIUM PROCESSORS)

The Pentium processor provides two 40-bit performance counters, which can be used to count events or measure 
duration. The counters are supported by three MSRs: the control and event select MSR (CESR) and the perfor-
mance counter MSRs (CTR0 and CTR1). These can be read from and written to using the RDMSR and WRMSR 
instructions, respectively. They can be accessed using these instructions only when operating at privilege level 0.