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All logical processors that are using the paging structures that are being modified must participate and perform 
appropriate invalidations after the modifications are made.

If the modifications to the paging-structure entries are made before the barrier or if there is no barrier, the 
operating system must ensure one of the following: (1) that the affected linear-address range is not used 
between the time of modification and the time of invalidation; or (2) that it is prepared to deal with the conse-
quences of the affected linear-address range being used during that period. For example, if the operating 
system does not allow pages being freed to be reallocated for another purpose until after the required invalida-
tions, writes to those pages by errant software will not unexpectedly modify memory that is in use.

Software must be prepared to deal with reads, instruction fetches, and prefetch requests to the affected linear-
address range that are a result of speculative execution that would never actually occur in the executed code 

When multiple logical processors are using the same linear-address space at the same time, they must coordinate 
before any request to modify the paging-structure entries that control that linear-address space. In these cases, 
the barrier in the TLB shootdown routine may not be required. For example, when freeing a range of linear 
addresses, some other mechanism can assure no logical processor is using that range before the request to free it 
is made. In this case, a logical processor freeing the range can clear the P flags in the PTEs associated with the 
range, free the physical page frames associated with the range, and then signal the other logical processors using 
that linear-address space to perform the necessary invalidations. All the affected logical processors must complete 
their invalidations before the linear-address range and the physical page frames previously associated with that 
range can be reallocated.



The architecture for virtual-machine extensions (VMX) includes features that interact with paging. Section 4.11.1 
discusses ways in which VMX-specific control transfers, called VMX transitions specially affect paging. Section 
gives an overview of VMX features specifically designed to support address translation.

4.11.1 VMX 


The VMX architecture defines two control transfers called VM entries and VM exits; collectively, these are called 
VMX transitions. VM entries and VM exits are described in detail in Chapter 26 and Chapter 27, respectively, in 
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C. The following items identify 
paging-related details:

VMX transitions modify the CR0 and CR4 registers and the IA32_EFER MSR concurrently. For this reason, they 
allow transitions between paging modes that would not otherwise be possible:
— VM entries allow transitions from IA-32e paging directly to either 32-bit paging or PAE paging.
— VM exits allow transitions from either 32-bit paging or PAE paging directly to IA-32e paging.

VMX transitions that result in PAE paging load the PDPTE registers (see Section 4.4.1) as follows:
— VM entries load the PDPTE registers either from the physical address being loaded into CR3 or from the 

virtual-machine control structure (VMCS); see Section

— VM exits load the PDPTE registers from the physical address being loaded into CR3; see Section 27.5.4.

VMX transitions invalidate the TLBs and paging-structure caches based on certain control settings. See Section 
and Section 27.5.5 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 


VMX Support for Address Translation

Chapter 28, “VMX Support for Address Translation,” in the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 3C
 describe two features of the virtual-machine extensions (VMX) that interact directly with 
paging. These are virtual-processor identifiers (VPIDs) and the extended page table mechanism (EPT).