Vol. 3A 10-39

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

10.12.1.3   Reserved Bit Checking

Section 10.12.1.2 and Table 10-6 specifies the reserved bit definitions for the APIC registers in x2APIC mode. Non-
zero writes (by WRMSR instruction) to reserved bits to these registers will raise a general protection fault exception 
while reads return zeros (RsvdZ semantics).
In x2APIC mode, the local APIC ID register is increased to 32 bits wide. This enables 2

32

–1 processors to be 

addressable in physical destination mode. This 32-bit value is referred to as “x2APIC ID”. A processor implementa-
tion may choose to support less than 32 bits in its hardware. System software should be agnostic to the actual 
number of bits that are implemented. All non-implemented bits will return zeros on reads by software. 
The APIC ID value of FFFF_FFFFH and the highest value corresponding to the implemented bit-width of the local 
APIC ID register in the system are reserved and cannot be assigned to any logical processor. 
In x2APIC mode, the local APIC ID register is a read-only register to system software and will be initialized by hard-
ware. It is accessed via the RDMSR instruction reading the MSR at address 0802H. 
Each logical processor in the system (including clusters with a communication fabric) must be configured with an 
unique x2APIC ID to avoid collisions of x2APIC IDs. On DP and high-end MP processors targeted to specific market 
segments and depending on the system configuration, it is possible that logical processors in different and “un-
connected” clusters power up initialized with overlapping x2APIC IDs. In these configurations, a model-specific 
means may be provided in those product segments to enable BIOS and/or platform firmware to re-configure the 

828H

280H

Error Status Register (ESR)

Read/write

WRMSR of a non-zero value causes 

#GP(0). See Section 10.5.3.

82FH

2F0H

LVT CMCI register

Read/write

See Figure 10-8 for reserved bits.

830H

4

300H and 310H

Interrupt Command Register 

(ICR)

Read/write

See Figure 10-28 for reserved bits

832H

320H

LVT Timer register

Read/write

See Figure 10-8 for reserved bits.

833H

330H

LVT Thermal Sensor register

Read/write

See Figure 10-8 for reserved bits.

834H

340H

LVT Performance Monitoring 

register

Read/write

See Figure 10-8 for reserved bits.

835H

350H

LVT LINT0 register

Read/write

See Figure 10-8 for reserved bits.

836H

360H

LVT LINT1 register

Read/write

See Figure 10-8 for reserved bits.

837H

370H

LVT Error register

Read/write

See Figure 10-8 for reserved bits.

838H

380H

Initial Count register (for 

Timer)

Read/write

839H

390H

Current Count register (for 

Timer)

Read-only

83EH

3E0H

Divide Configuration Register 

(DCR; for Timer)

Read/write

See Figure 10-10 for reserved bits.

83FH

Not available

SELF IPI

5

Write-only

Available only in x2APIC mode.

NOTES:

1. WRMSR causes #GP(0) for read-only registers.
2. WRMSR causes #GP(0) for attempts to set a reserved bit to 1 in a read/write register (including bits 63:32 of each register).
3. RDMSR causes #GP(0) for write-only registers.
4. MSR 831H is reserved; read/write operations cause general-protection exceptions. The contents of the APIC register at MMIO offset 

310H are accessible in x2APIC mode through the MSR at address 830H.

5. SELF IPI register is supported only in x2APIC mode.

Table 10-6. Local APIC Register Address Map Supported by x2APIC (Contd.)

MSR Address 

(x2APIC mode)

MMIO Offset 

(xAPIC mode)

Register Name

MSR R/W 

Semantics

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