36-34 Vol. 3C

INTEL® PROCESSOR TRACE

normal binding and ordering rules that apply to these packets outside of PSB+ can be ignored when these packets 
are between a PSB and PSBEND. They inform the decoder of the state of the processor at the time of the PSB.
PSB+ can include:

•

Timestamp (TSC), if IA32_RTIT_CTL.TSCEn=1. 

•

Timestamp-MTC Align (TMA), if IA32_RTIT_CTL.TSCEn=1 && IA32_RTIT_CTL.MTCEn=1.

•

Paging Info Packet (PIP), if ContextEn=1 and IA32_RTIT_CTL.OS=1. The non-root bit (NR) is set if the logical 
processor is in VMX non-root operation and the “conceal VMX non-root operation from Intel PT”. VM-execution 
control is 0.

•

VMCS packet, if either the logical is in VMX root operation or the logical processor is in VMX non-root operation 
and the “conceal VMX non-root operation from Intel PT” VM-execution control is 0.

•

Core Bus Ratio (CBR).

•

MODE.TSX, if ContextEn=1 and BranchEn = 1. 

•

MODE.Exec, if PacketEn=1. 

•

Flow Update Packet (FUP), if PacketEn=1.

PSB is generated only when TriggerEn=1; hence PSB+ has the same dependencies. The ordering of packets within 
PSB+ is not fixed. Timing packets such as CYC and MTC may be generated between PSB and PSBEND, and their 
meanings are the same as outside PSB+.
Note that an overflow can occur during PSB+, and this could cause the PSBEND packet to be lost. For this reason, 
the OVF packet should also be viewed as terminating PSB+.

36.3.8 

Internal Buffer Overflow

In the rare circumstances when new packets need to be generated but the processor’s dedicated internal buffers 
are all full, an “internal buffer overflow” occurs. On such an overflow packet generation ceases (as packets would 
need to enter the processor’s internal buffer) until the overflow resolves. Once resolved, packet generation 
resumes.
When the buffer overflow is cleared, an OVF packet (Section 36.4.2.16) is generated, and the processor ensures 
that packets which follow the OVF are not compressed (IP compression or RET compression) against packets that 
were lost. 
If IA32_RTIT_CTL.BranchEn = 1, the OVF packet will be followed by a FUP if the overflow resolves while Pack-
etEn=1. If the overflow resolves while PacketEn = 0 no packet is generated, but a TIP.PGE will naturally be gener-
ated later, once PacketEn = 1. The payload of the FUP or TIP.PGE will be the Current IP of the first instruction upon 
which tracing resumes after the overflow is cleared. Between the OVF and following FUP or TIP.PGE, there may be 
packets that do not depend on PacketEn, such as timing packets. If the overflow resolves while PacketEn=0, other 
packets that are not dependent on PacketEn may come before the TIP.PGE. 

36.3.8.1   Overflow Impact on Enables

The address comparisons to ADDRn ranges, for IP filtering and TraceStop (Section 36.2.4.3), continue during a 
buffer overflow, and TriggerEn, ContextEn, and FilterEn may change during a buffer overflow. Like other packets, 
however, any TIP.PGE or TIP.PGD packets that would have been generated will be lost. Further, 
IA32_RTIT_STATUS.PacketByteCnt will not increment, since it is only incremented when packets are generated.
If a TraceStop event occurs during the buffer overflow, IA32_RTIT_STATUS.Stopped will still be set, tracing will 
cease as a result. However, the TraceStop packet, and any TIP.PGD that result from the TraceStop, may be 
dropped.

36.3.8.2   Overflow Impact on Timing Packets

Any timing packets that are generated during a buffer overflow will be dropped. If only a few MTC packets are 
dropped, a decoder should be able to detect this by noticing that the time value in the first MTC packet after the 
buffer overflow incremented by more than one. If the buffer overflow lasted long enough that 256 MTC packets are 
lost (and thus the MTC packet ‘wraps’ its 8-bit CTC value), then the decoder may be unable to properly understand