6-48 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

Interrupt 19—SIMD Floating-Point Exception (#XM)

Exception Class

Fault.

Description

Indicates the processor has detected an SSE/SSE2/SSE3 SIMD floating-point exception. The appropriate status 
flag in the MXCSR register must be set and the particular exception unmasked for this interrupt to be generated.
There are six classes of numeric exception conditions that can occur while executing an SSE/ SSE2/SSE3 SIMD 
floating-point instruction:

•

Invalid operation (#I)

•

Divide-by-zero (#Z)

•

Denormal operand (#D)

•

Numeric overflow (#O)

•

Numeric underflow (#U)

•

Inexact result (Precision) (#P)

The invalid operation, divide-by-zero, and denormal-operand exceptions are pre-computation exceptions; that is, 
they are detected before any arithmetic operation occurs. The numeric underflow, numeric overflow, and inexact 
result exceptions are post-computational exceptions.
See “SIMD Floating-Point Exceptions” in Chapter 11 of the Intel® 64 and IA-32 Architectures Software Developer’s 
Manual, Volume 1, for additional information about the SIMD floating-point exception classes.
When a SIMD floating-point exception occurs, the processor does either of the following things:

•

It handles the exception automatically by producing the most reasonable result and allowing program 
execution to continue undisturbed. This is the response to masked exceptions.

•

It generates a SIMD floating-point exception, which in turn invokes a software exception handler. This is the 
response to unmasked exceptions.

Each of the six SIMD floating-point exception conditions has a corresponding flag bit and mask bit in the MXCSR 
register. If an exception is masked (the corresponding mask bit in the MXCSR register is set), the processor takes 
an appropriate automatic default action and continues with the computation. If the exception is unmasked (the 
corresponding mask bit is clear) and the operating system supports SIMD floating-point exceptions (the OSXM-
MEXCPT flag in control register CR4 is set), a software exception handler is invoked through a SIMD floating-point 
exception. If the exception is unmasked and the OSXMMEXCPT bit is clear (indicating that the operating system 
does not support unmasked SIMD floating-point exceptions), an invalid opcode exception (#UD) is signaled instead 
of a SIMD floating-point exception.
Note that because SIMD floating-point exceptions are precise and occur immediately, the situation does not arise 
where an x87 FPU instruction, a WAIT/FWAIT instruction, or another SSE/SSE2/SSE3 instruction will catch a 
pending unmasked SIMD floating-point exception.
In situations where a SIMD floating-point exception occurred while the SIMD floating-point exceptions were 
masked (causing the corresponding exception flag to be set) and the SIMD floating-point exception was subse-
quently unmasked, then no exception is generated when the exception is unmasked.
When SSE/SSE2/SSE3 SIMD floating-point instructions operate on packed operands (made up of two or four sub-
operands), multiple SIMD floating-point exception conditions may be detected. If no more than one exception 
condition is detected for one or more sets of sub-operands, the exception flags are set for each exception condition 
detected. For example, an invalid exception detected for one sub-operand will not prevent the reporting of a divide-
by-zero exception for another sub-operand. However, when two or more exceptions conditions are generated for 
one sub-operand, only one exception condition is reported, according to the precedences shown in Table 6-8. This 
exception precedence sometimes results in the higher priority exception condition being reported and the lower 
priority exception conditions being ignored.