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Vol. 3C 25-5


— The value of ECX is in the range C0000000H – C0001FFFH and bit n in write bitmap for high MSRs is 1, 

where n is the value of ECX & 00001FFFH.

See Section 24.6.9 for details regarding how these bitmaps are identified.

XRSTORS. The XRSTORS instruction causes a VM exit if the “enable XSAVES/XRSTORS” VM-execution control 
is 1and any bit is set in the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the 
XSS-exiting bitmap (see Section 24.6.19).

XSAVES. The XSAVES instruction causes a VM exit if the “enable XSAVES/XRSTORS” VM-execution control is 
1 and any bit is set in the logical-AND of the following three values: EDX:EAX, the IA32_XSS MSR, and the XSS-
exiting bitmap (see Section 24.6.19).



In addition to VM exits caused by instruction execution, the following events can cause VM exits:

Exceptions. Exceptions (faults, traps, and aborts) cause VM exits based on the exception bitmap (see Section 
 If an exception occurs, its vector (in the range 0–31) is used to select a bit in the exception bitmap. If 
the bit is 1, a VM exit occurs; if the bit is 0, the exception is delivered normally through the guest IDT. This use 
of the exception bitmap applies also to exceptions generated by the instructions INT3, INTO, BOUND, and UD2.
Page faults (exceptions with vector 14) are specially treated. When a page fault occurs, a processor consults 
(1) bit 14 of the exception bitmap; (2) the error code produced with the page fault [PFEC]; (3) the page-fault 
error-code mask field [PFEC_MASK]; and (4) the page-fault error-code match field [PFEC_MATCH]. It checks if 
PFEC & PFEC_MASK = PFEC_MATCH. If there is equality, the specification of bit 14 in the exception bitmap is 
followed (for example, a VM exit occurs if that bit is set). If there is inequality, the meaning of that bit is 
reversed (for example, a VM exit occurs if that bit is clear).
Thus, if software desires VM exits on all page faults, it can set bit 14 in the exception bitmap to 1 and set the 
page-fault error-code mask and match fields each to 00000000H. If software desires VM exits on no page 
faults, it can set bit 14 in the exception bitmap to 1, the page-fault error-code mask field to 00000000H, and 
the page-fault error-code match field to FFFFFFFFH.

Triple fault. A VM exit occurs if the logical processor encounters an exception while attempting to call the 
double-fault handler and that exception itself does not cause a VM exit due to the exception bitmap. This 
applies to the case in which the double-fault exception was generated within VMX non-root operation, the case 
in which the double-fault exception was generated during event injection by VM entry, and to the case in which 
VM entry is injecting a double-fault exception.

External interrupts. An external interrupt causes a VM exit if the “external-interrupt exiting” VM-execution 
control is 1. (See Section 25.6 for an exception.) Otherwise, the interrupt is delivered normally through the 
IDT. (If a logical processor is in the shutdown state or the wait-for-SIPI state, external interrupts are blocked. 
The interrupt is not delivered through the IDT and no VM exit occurs.)

Non-maskable interrupts (NMIs). An NMI causes a VM exit if the “NMI exiting” VM-execution control is 1. 
Otherwise, it is delivered using descriptor 2 of the IDT. (If a logical processor is in the wait-for-SIPI state, NMIs 
are blocked. The NMI is not delivered through the IDT and no VM exit occurs.)

INIT signals. INIT signals cause VM exits. A logical processor performs none of the operations normally 
associated with these events. Such exits do not modify register state or clear pending events as they would 
outside of VMX operation. (If a logical processor is in the wait-for-SIPI state, INIT signals are blocked. They do 
not cause VM exits in this case.)

Start-up IPIs (SIPIs). SIPIs cause VM exits. If a logical processor is not in the wait-for-SIPI activity state 
when a SIPI arrives, no VM exit occurs and the SIPI is discarded. VM exits due to SIPIs do not perform any of 
the normal operations associated with those events: they do not modify register state as they would outside of 
VMX operation. (If a logical processor is not in the wait-for-SIPI state, SIPIs are blocked. They do not cause 
VM exits in this case.)

Task switches. Task switches are not allowed in VMX non-root operation. Any attempt to effect a task switch 
in VMX non-root operation causes a VM exit. See Section 25.4.2.

System-management interrupts (SMIs). If the logical processor is using the dual-monitor treatment of 
SMIs and system-management mode (SMM), SMIs cause SMM VM exits. See Section 34.15.2.