Vol. 3B 14-15

POWER AND THERMAL MANAGEMENT

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HDC_Allow_Block (bit 0, R/W) — Software sets this bit to allow this logical processors to honor the 
package-level IA32_PKG_HDC_CTL.HDC_PKG_Enable control. Clearing this bit prevents this logical processor 
from using the HDC. This bit is writable only if CPUID.06H:EAX[bit 13] = 1. Default = one (1). 

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Bits 63:1 are reserved and must be zero.

Fine-grain OS control of HDC operation at the granularity of per-logical-processor is provided by IA32_PM_CTL1. 
At RESET, all logical processors are allowed to participate in HDC operation such that OS can manage HDC using 
the package-level IA32_PKG_HDC_CTL.
Writes to IA32_PM_CTL1 complete with the latency that is typical to WRMSR to a Logical Processor level MSR. 
When the OS chooses to manage HDC operation at per-logical-processor granularity, it can write to IA32_PM_CTL1 
on one or more logical processors as desired. Each write to IA32_PM_CTL1 must be done by code that executes on 
the logical processor targeted to be allowed into or blocked from HDC operation. 
Blocking one logical processor for HDC operation may have package level impact. For example, the processor may 
decide to stop duty cycling of all other Logical Processors as well. 
The propagation of IA32_PKG_HDC_CTL.HDC_PKG_Enable in a package takes longer than a WRMSR to 
IA32_PM_CTL1. The last completed write to IA32_PM_CTL1 on a logical processor will be honored when a ‘0’-to-’1’ 
transition of IA32_PKG_HDC_CTL.HDC_PKG_Enable arrives to a logical processor.

14.5.4 

HDC Residency Counters

There is a collection of counters available for software to track various residency metrics related to HDC operation. 
In general, HDC residency time is defined as the time in HDC forced idle state at the granularity of per-logical-
processor, per-core, or package. At the granularity of per-core/package-level HDC residency, at least one of the 
logical processor in a core/package must be in the HDC forced idle state.

14.5.4.1   IA32_THREAD_STALL

Software can track per-logical-processor HDC residency using the architectural MSR IA32_THREAD_STALL.The 
layout of the IA32_THREAD_STALL MSR is shown in Figure 14-14. Each logical processor in a package has its own 
IA32_THREAD_STALL MSR. The bit fields are described below: 

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Stall_Cycle_Cnt (bits 63:0, R/O) — Stores accumulated HDC forced-idle cycle count of this processor core 
since last RESET. This counter increments at the same rate of the TSC. The count is updated only after the 
logical processor exits from the forced idled C-state. At each update, the number of cycles that the logical 
processor was stalled due to forced-idle will be added to the counter. This counter is available only if 
CPUID.06H:EAX[bit 13] = 1. Default = zero (0). 

Figure 14-13.  IA32_PM_CTL1 MSR

Figure 14-14.  IA32_THREAD_STALL MSR

63

0

Reserved

1

HDC_Allow_Block

Reserved

63

0

Stall_cycle_cnt