29-4 Vol. 3C

APIC VIRTUALIZATION AND VIRTUAL INTERRUPTS

29.1.4, Section 29.1.5, and Section 29.6 for details of when evaluation of pending virtual interrupts is performed. 
No other operations cause the evaluation of pending virtual interrupts, even if they modify RVI or VPPR.
Evaluation of pending virtual interrupts uses the guest interrupt status (specifically, RVI; see Section 24.4.2). The 
following pseudocode details the evaluation of pending virtual interrupts:

IF “interrupt-window exiting” is 0 AND
RVI[7:4] > VPPR[7:4] (see Section 29.1.1 for definition of VPPR)

THEN recognize a pending virtual interrupt;

ELSE

do not recognize a pending virtual interrupt;

FI;

Once recognized, a virtual interrupt may be delivered in VMX non-root operation; see Section 29.2.2.
Evaluation of pending virtual interrupts is caused only by VM entry, TPR virtualization, EOI virtualization, self-IPI 
virtualization, and posted-interrupt processing. No other operations do so, even if they modify RVI or VPPR. The 
logical processor ceases recognition of a pending virtual interrupt following the delivery of a virtual interrupt.

29.2.2 Virtual-Interrupt 

Delivery

If a virtual interrupt has been recognized (see Section 29.2.1), it is delivered at an instruction boundary when the 
following conditions all hold: (1) RFLAGS.IF = 1; (2) there is no blocking by STI; (3) there is no blocking by MOV 
SS or by POP SS; and (4) the “interrupt-window exiting” VM-execution control is 0.
Virtual-interrupt delivery has the same priority as that of VM exits due to the 1-setting of the “interrupt-window 
exiting” VM-execution control.

2

 Thus, non-maskable interrupts (NMIs) and higher priority events take priority over 

delivery of a virtual interrupt; delivery of a virtual interrupt takes priority over external interrupts and lower priority 
events.
Virtual-interrupt delivery wakes a logical processor from the same inactive activity states as would an external 
interrupt. Specifically, it wakes a logical processor from the states entered using the HLT and MWAIT instructions. 
It does not wake a logical processor in the shutdown state or in the wait-for-SIPI state.
Virtual-interrupt delivery updates the guest interrupt status (both RVI and SVI; see Section 24.4.2) and delivers an 
event within VMX non-root operation without a VM exit. The following pseudocode details the behavior of virtual-
interrupt delivery (see Section 29.1.1 for definition of VISR, VIRR, and VPPR):

Vector ← RVI;

VISR[Vector] ← 1;

SVI ← Vector;

VPPR ← Vector & F0H;

VIRR[Vector] ← 0;

IF any bits set in VIRR

THEN RVI ← highest index of bit set in VIRR

ELSE RVI ← 0;

FI;
deliver interrupt with Vector through IDT;
cease recognition of any pending virtual interrupt;

If a logical processor is in enclave mode, an Asynchronous Enclave Exit (AEX) occurs before delivery of a virtual 
interrupt (see Chapter 40, “Enclave Exiting Events”).

2. A logical processor never recognizes or delivers a virtual interrupt if the “interrupt-window exiting” VM-execution control is 1. 

Because of this, the relative priority of virtual-interrupt delivery and VM exits due to the 1-setting of that control is not defined.