18-54 Vol. 3B

PERFORMANCE MONITORING

Only IA32_PMC0 through IA32_PMC3 support PEBS. 

NOTE

PEBS events are only valid when the following fields of IA32_PERFEVTSELx are all zero: AnyThread, 
Edge, Invert, CMask.

In a PMU with PDIR capability, PEBS behavior is unpredictable if IA32_PERFEVTSELx or IA32_PMCx 
is changed for a PEBS-enabled counter while an event is being counted. To avoid this, changes to 
the programming or value of a PEBS-enabled counter should be performed when the counter is 
disabled.

In IA32_PEBS_ENABLE MSR, bit 63 is defined as PS_ENABLE: When set, this enables IA32_PMC3 to capture 
precise store information. Only IA32_PMC3 supports the precise store facility. In typical usage of PEBS, the bit 
fields in IA32_PEBS_ENABLE are written to when the agent software starts PEBS operation; the enabled bit fields 
should be modified only when re-programming another PEBS event or cleared when the agent uses the perfor-
mance counters for non-PEBS operations. 

18.9.4.1   PEBS Record Format

The layout of PEBS records physically identical to those shown in Table 18-23, but the fields at offset 98H, A0H and 
A8H have been enhanced to support additional PEBS capabilities.

•

Load/Store Data Linear Address (Offset 98H): This field will contain the linear address of the source of the load, 
or linear address of the destination of the store.

•

Data Source /Store Status (Offset A0H):When load latency is enabled, this field will contain three piece of 
information (including an encoded value indicating the source which satisfied the load operation). The source 
field encodings are detailed in Table 18-24. When precise store is enabled, this field will contain information 
indicating the status of the store, as detailed in Table 19.

•

Latency Value/0 (Offset A8H): When load latency is enabled, this field contains the latency in cycles to service 
the load. This field is not meaningful when precise store is enabled and will be written to zero in that case. Upon 
writing the PEBS record, microcode clears the overflow status bits in the IA32_PERF_GLOBAL_STATUS corre-
sponding to those counters that both overflowed and were enabled in the IA32_PEBS_ENABLE register. The 
status bits of other counters remain unaffected.

The number PEBS events has expanded. The list of PEBS events supported in Intel microarchitecture code name 
Sandy Bridge is shown in Table 18-32.

Figure 18-35.  Layout of IA32_PEBS_ENABLE MSR 

LL_EN_PMC3 (R/W)
LL_EN_PMC2 (R/W)

8 7

0

LL_EN_PMC1 (R/W)

32

3

33

1

Reserved

63

2

4

31

5

6

34

35

36

PEBS_EN_PMC3 (R/W)
PEBS_EN_PMC2 (R/W)
PEBS_EN_PMC1 (R/W)
PEBS_EN_PMC0 (R/W)

LL_EN_PMC0 (R/W)

RESET Value — 00000000_00000000H

62

PS_EN (R/W)